Renesas' Upward-Compatible H8SX Series 32-bit CISC Microcontrollers Offer Nearly Three Times the Processing Power of Previous 16-bit H8S Chips.Business Editors/High-Tech Writers Embedded Systems Embedded systems Computer systems that cannot be programmed by the user because they are preprogrammed for a specific task and are buried within the equipment they serve. Conference San Francisco San Francisco (săn frănsĭs`kō), city (1990 pop. 723,959), coextensive with San Francisco co., W Calif., on the tip of a peninsula between the Pacific Ocean and San Francisco Bay, which are connected by the strait known as the Golden 2003 SAN FRANCISCO--(BUSINESS WIRE)--April 21, 2003 The New Core Can Reduce Code Size by 17 Percent When Compared to the Current H8S Core, Thus Saving Memory Space and Enhancing Performance at Lower Costs Renesas Technology Renesas Technology Corporation (ルネサス テクノロジ| America, Inc. -- a U.S. subsidiary of the new joint-venture semiconductor company established by Hitachi, Ltd. and Mitsubishi Electric Mitsubishi Electric Corporation (三菱電機株式会社 Corporation with the world's top microcontroller (MCU (1) (MicroController Unit) A computer on a single chip. See microcontroller. (2) (Multipoint Control Unit) A device that is used to moderate a videoconference of three or more end points (users at computers or groups of users ) market share -- today introduced the 32-bit H8SX architecture, a high-performance CISC (Complex Instruction Set Computer) Pronounced "sisk." The traditional architecture of a computer which uses microcode to execute very comprehensive instructions. CPU CPU in full central processing unit Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. core with an on-chip multiplier and a divider for a wide range of applications such as PC peripherals and industrial products. Built with a 0.18 micron CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. process, the H8SX architecture can deliver 48 DMIPS DMIPS Dhrystone MIPS (Million Instructions Per Second) (Dhrystone million instructions per second Noun 1. million instructions per second - (computer science) a unit for measuring the execution speed of a computer's CPU (but not the whole system); "4 MIPS is 4,000,000 instructions per second" MIPS ) performance and achieve a maximum operating frequency of 48 Megahertz One million cycles per second. See MHz. MegaHertz - (MHz) Millions of cycles per second. The unit of frequency used to measure the clock rate of modern digital logic, including microprocessors. (MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. ). It has an external bus of 32 bits wide, a built-in multiply/divide function, and an optimized instruction set. As a result, the new architecture can provide an almost threefold improvement in processing power compared to Renesas' current 16-bit H8S CPU core, with which it is upward-compatible. High Performance, Improved Code Efficiency, Enhanced On-Chip Peripherals According to according to prep. 1. As stated or indicated by; on the authority of: according to historians. 2. In keeping with: according to instructions. 3. Hank Pawlowicz, product marketing manager of the system LSI LSI: see integrated circuit. (Large Scale Integration) Between 3,000 and 100,000 transistors on a chip. See SSI, MSI, VLSI and ULSI. business unit, Renesas Technology America, Inc., "The new H8SX architecture provides higher performance, better code efficiency and faster access to external memory than the standard H8S core. It is also upward compatible See forward compatible. with our existing H8 family of MCUs, hence providing easy migration to higher-end products." To simplify connectivity to peripheral devices, the H8SX architecture incorporates a function for converting data to little-endian format and an address/data multiplex bus I/O interface See port and expansion slot. that can be set for each area of an external device. These enhancements allow system designs that have fewer external parts. They also reduce the software load. Reduced Code Size and Improved Performance Aside from its speed advantages, the new core also addresses the needs for cost-sensitive systems by providing improved code efficiency. The H8SX architecture has 18 new instructions (87, total) and 3 more addressing modes (11, total). By utilizing these new instructions, the H8SX core typically reduces the size of application code by 17 percent. The smaller code size allows more programs to fit into the available memory. Moreover, the architecture's expanded address space, up to 4 GB, accommodates the larger programs and increased data sizes used by embedded systems that provide greater functionality. First H8SX Device: The H8SX/1650 MCU Renesas also introduced the first device with the H8SX core: the H8SX/1650, a ROMless MCU for price-sensitive applications. It has a 35 MHz maximum operating frequency and achieves an excellent balance between cost and performance. Operating at 35 MHz, the MCU has a minimum instruction execution time of 28.6 nanoseconds (ns). It delivers 35DMIPS -- more than twice the processing throughput of a 33 MHz H8S MCU -- enabling high-performance systems at lower cost than alternative chips. Packaged in a 120-pin thin QFP (Quad FlatPack) A square, surface mount chip package that has leads on all four sides and comes in several varieties. PQFP (Plastic QFP) may refer to all of the following QFP types. All quad flatpacks use gull-wing leads, except for the CQFP, which stick straight out. package, the H8SX/1650 MCU provides 24 KB of RAM and a useful set of peripheral functions. These include an external bus state controller (BSC (Binary Synchronous Communications) See bisync. ); data transfer controller (DTC DTC See: Depository Transfer Check DTC See: Depository Trust Company DTC See Depository Trust Company (DTC). , a better alternative to DMA (1) (Digital Media Adapter) See digital media hub. (2) (Document Management Alliance) A specification that provides a common interface for accessing and searching document databases. controller); 6-channel timer pulse unit (TPU TPU - Text Processing Utility ) with rich set of features such as input capture, output compare, PWM (Pulse Width Modulation) A modulation technique that generates variable-width pulses to represent the amplitude of an analog input signal. Like its fixed-width pulse density modulation (PDM) cousin, the output switching transistor is on more of the time for a output; and more. Roadmap for Next-Generation MCUs During the development of the new 32-bit CISC architecture, Renesas chip designers built an engineering test chip containing many of the peripheral functions that could be offered in future H8SX devices. The test chip in a 600-bump BGA (Ball Grid Array) A popular surface mount chip package that uses a grid of solder balls as its connectors. Available in plastic and ceramic varieties, BGA is noted for its compact size, high lead count and low inductance, which allows lower voltages to be used. package has an 8/16/32-bit external bus, 64 KB of RAM and a 16-MB or 256-MB external address space. Future devices in H8SX series will consist of standard MCUs and application-specific standard products (ASSPs). The standard MCUs will offer up to 1 MB of on-chip ROM, enhanced peripherals and support for in-circuit emulation. The ASSPs will be optimized for key market segments such as PC peripherals and automotive systems See ITS, embedded system, drive-by-wire, adaptive cruise control, collision avoidance system, autonomous vehicle, heads-up display, DSRC, lane departure system, CAN bus, FlexRay and SYNC. . They will integrate specialized peripherals such as on-chip USB USB in full Universal Serial Bus Type of serial bus that allows peripheral devices (disks, modems, printers, digitizers, data gloves, etc.) to be easily connected to a computer. (2.0) functions and controller area network (CAN) interfaces. Systems Development Tools Renesas is developing the powerful, fully-featured E6000H in-circuit emulator See ICE. to aid the development of embedded systems that use the H8SX/1650 MCU or future products in the H8SX series. Additionally Renesas will offer the High-performance Embedded Workshop (HEW), a flexible code development environment with fully integrated software tools (editor, C compiler, assembler, linker, librarian and simulator). The E6000H emulator will be available in Q2 2003 and the HEW will be available in July 2003. Price and Availability H8SX/1650 MCU Renesas Part Package Quantity Price/Availability (Evaluation Chip) Number ---------------------------------------------------------------------- 35 MHz/3.3 V HD6411650 TQFP-120 Samples $7.00/ ROMless April 2003 microcomputer ---------------------------------------------------------------------- Reader Contact Readers can find additional product and contact information on the Renesas Technology Web site at http://www.renesas.com/eng/products/mpumcu/32bit/h8sx/index.html or by calling 408/433-1990. About Renesas Technology Corp. Renesas Technology Corp. designs and manufactures highly integrated semiconductor system solutions for mobile, networking, automotive, industrial and digital home electronics markets. Established on April 1, 2003, as a joint venture between Hitachi, Ltd. (TSE See Tokyo Stock Exchange. TSE 1. See Tokyo Stock Exchange (TSE). 2. See Toronto Stock Exchange (TSE). :6501, NYSE NYSE See: New York Stock Exchange :HIT) and Mitsubishi Electric Corporation (TSE:6503) and headquartered in Tokyo, Japan, Renesas Technology is one of the largest semiconductor companies in the world and the number one microcontroller supplier globally. Besides microcontrollers, Renesas Technology offers system-on-chip devices, Smart Card ICs, mixed-signal products, flash memories, SRAMs and more. www.renesas.com Note: A specification summary is included in this release, and a block diagram of the H8SX/1650 microcontroller is available.
Specifications: Renesas H8SX/1650 MCU and Engineering Test Chip
Item H8SX/1650 (HD6411650) Engineering Test Chip
----------------------------------------------------------------------
CPU core 32-bit H8SX core
----------------------------------------------------------------------
Operating frequency 35MHz 48MHz
(max.)
----------------------------------------------------------------------
Power supply voltage 3.0 V to 3.6 V 3.0 V to 3.6 V
----------------------------------------------------------------------
On-chip RAM 24 Kbytes 64 Kbytes
----------------------------------------------------------------------
External address space 16 Mbytes 16 Mbytes, 256 Mbytes
----------------------------------------------------------------------
External bus width 8/16 bits 8/16/32 bits
----------------------------------------------------------------------
Calculation functions On-chip multiplier, divider, multiply-and-
accumulate processor
----------------------------------------------------------------------
Bus state controller ROM, SRAM, burst ROM, ROM, SRAM, DRAM,
byte-control SRAM synchronous DRAM,
directly connectable burst ROM, byte-
control SRAM directly
connectable
----------------------------------------------------------------------
Key new features Address/data multiplex I/O interface settable
area by area
------------------------------------------------
Endian conversion function for connection of
little-endian devices
----------------------------------------------------------------------
On-chip peripheral DMA controller (DMAC)
functions -- x 4 channels
------------------------------------------------
-- External DMA controller
(EXDMAC)
x 4 channels
------------------------------------------------
Data transfer Data transfer
controller (DTC) controller (DTC)
------------------------------------------------
Timer pulse unit (TPU) Timer pulse unit (TPU)
x 6 channels x 12 channels
------------------------------------------------
Programmable pulse generator (PPG)
------------------------------------------------
-- Multifunction timer
unit (MTU)
x 5 channels
------------------------------------------------
8-bit timer (MTR) x 4 8-bit timer (MTR) x 8
channels channels
-----------------------------------------------
Watchdog timer (WDT) x Watchdog timer (WDT) x
1 channel 1 channel
------------------------------------------------
-- Advanced user debugger
(AUD)
------------------------------------------------
-- Hitachi user debug
interface (H-UDI)
------------------------------------------------
Serial communication Serial communication
interface interface
x 4 channels x 6 channels
------------------------------------------------
-- Serial communication
interface with FIFO x
1 channel
------------------------------------------------
-- I2C bus interface x 2
channels
------------------------------------------------
A/D converter (10-bit A/D converter (10-bit
resolution) resolution)
x 8 channels x 16 channels
------------------------------------------------
D/A converter (8-bit D/A converter (8-bit
resolution) resolution)
x 2 channels x 6 channels
------------------------------------------------
Clock pulse generator Clock pulse generator
(CPG): Built-in (CPG): Built-in
multiplication PLL multiplication PLL
----------------------------------------------------------------------
Power-down modes 6 modes: Sleep, Software Standby, Hardware
Standby, Module Stop, All Modules Clock Stop,
and Multi Clock
----------------------------------------------------------------------
Package TQFP-120 BGA-600
----------------------------------------------------------------------
|
|
||||||||||||||||

Printer friendly
Cite/link
Email
Feedback
Reader Opinion