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Registration techniques for advanced technology PCBs: or, so you think you can really do two-track routing?

This article will review all of the essential steps involved in the proper registration of today's advanced technology printed circuits. We've included a registration template that will help PCB manufacturers grade the capabilities within their own factory, and we'll discuss steps needed to improve the aptitude of the systems and processes.

The correct registration and alignment of through-holes, blind and buried vias, and soldermask to the innerlayer and outerlayer pads is becoming increasingly difficult with today's tight pitch product, especially on high layer-count boards and/or large form-factor PCs. Include HDI, sequential lamination, via-in-pad and other complex design requirements and you assure a challenge to a facility's registration process.

Many producers of PCBs do not fully realize all of the processes that contribute to registering a board for dense-featured ASICs and tight trace spacing. Telecommunication products--with their high layers and large panel sizes--are adding 0.8 mm and 0.5 mm pitch devices into their designs. To improve signal speed and keep the size of the cabinets within spec, they are looking to introduce two-track routing between the BGA/CCGA pads.

The latest movements into dense routing techniques have moved the potential drill-to-metal CAF concerns into the forefront, ahead of drill-to-drill CAF potential. Low CAF and non-CAF materials may help with this concern, but these will also increase material costs. In the past, breakout and annular ring requirements were for holewall reliability concerns. Now the annular ring requirement is an inviolable reference for potential CAF concerns.

Before getting into specific areas of influence, it is important to understand what is involved in registration, specifically innerlayer registration to the primary drill process. The best way to start on a plan of continuous improvement is by bucketing each area, then measuring and calculating the influence. Many PCB manufacturers simply add the tolerances of the equipment purchased to complete the registration process and call the rest of the variance "material movement."

Some key areas that can influence registration but are frequently ignored are:

The rate of rise monitoring of the PCBs in lamination (not platen temperature). Trying to adjust for scaling influences without monitoring this process creates a constant movement of the material influence target.

Drill depth into backup (small holes). The registration influence can't be measured by a manual caliper (visual depth scope), but the drill wander influence can be measured.

Incorrect scaling influences due to scripting errors by CAM operators. This is a frequent issue if the entire scaling scripts are not completely automated. A small typo can change the scaling script to zero, but still show scale values on the film.

Two-camera PEP alignment without slope compensation. The suppliers of this technology have been trying for years to get PCB manufacturers to upgrade, but the old equipment in many shops was purchased used, without much real understanding of the process and limitations. If the targets are offset in one axis (as is the case in the most popular models), then a scaling influence reset is required or a shift will occur. The PEP will not capture this shift.

Hard and soft tooling influences in drilling. While hard tooling has the advantage of being automated, without vision alignment to the drill head, it does add additional variation.

Use of post-lamination x-ray systems incorrectly or not understanding resolution vs. accuracy. Trying to register multiple depths of innerlayers at once without understanding what resolution error is involved is a common pitfall.

Lead time after scaling. This must be minimized and consistently controlled, especially in high-heat, high-humidity environments. Frequently, the cores will "grow" with time, and correct scaling today may mean misregistration of the PCB if those cores are allowed to sit for hours or days before processing.

Along with a complete sequencing of each step in the manufacturing process, we can highlight their influences on high-density registration, as well as inform the process engineer of the consequences of using sub-par systems for the task at hand. First, though, we should begin with an understanding of the OEM's registration requirements and the reasoning involved in the specifications.

The first requirement is for accurate registration of the holes to their pads. Usually, there is an annular ring requirement or a spec that at least demands tangency. Advanced technology OEMs demand an annular ring of 1 mil. This further tightens the registration constraints of the job.

For example: if the design utilizes a 1.00 mm BGA pitch (which typically uses a 10 mil drilled hole on a 19 mil pad), and there is a 1 mil annular ring condition that must be followed, it reduces the hole-to-pad allowances by 2 mils (FIGURE 1).


Many advanced routing designs ignore etch compensation with drill-to-metal concerns. (Drill-to-metal refers to the distance from the edge of a drilled hole to the nearest metal feature). Just routing with a 4 mil line doesn't truly achieve the actual drill-to-metal specifics. First, complete the stackup line width objective, then use that value (with etch compensation) for routing.

Frequently, CAF resistance concerns demand a second necessity for a minimum drill-to-metal spec. With telecom or workstation products, this spec can be as little as 9 to 11 mils (FIGURE 2). If you produce a PCB designed with a drill-to-metal tolerance of 8.5 mils and your registration error is off by as little as 4 mils, the PCB will often be rejected--many OEMs regard a drill-to-metal spacing of 5 mils as a fire hazard. This can be extremely difficult to manufacture with large panel sizes.


Another important aspect of registration regarding PCB design is the line width and spacing width between BGA pads for internal routing purposes. For a 1.0 mm BGA device, it is typical to see two-track routing of lines between the pads on internal layers. With today's line and spacing size processing averages of 4/4 for innerlayers, this makes proper registration paramount when building boards with these features (FIGURE 3).


If your registration is off by only 1.5 mils across the panel, then you are close to violating the drill-to-metal constraint of 8.5 mils. PCB designers would also like to shrink designs down to 0.8 mm pitch devices with two-track routing but, to date, printed circuit suppliers are incapable of producing sub-3 mil lines and spaces. And with today's laminates, they are reticent to build boards with drill-to-metal spacings of less than 7 mils.

TABLE 1 lists all the processes involved in assuring proper registration. Many PCB makers concentrate on only a few of these items, often finding it hard to understand why they cannot significantly improve their registration limitations. To put it bluntly: Pin lamination and accurate punching of the tooling holes are not the end-all to improving registration capabilities. Without giving away any special techniques for registration, simply being able to measure the variance is a huge step in the right direction.

Registration Hot Spots

One of the most difficult changes made at a PCB facility is with the alignment process during any of the innerlayer manufacturing steps. Visual validation in the outerlayer processes makes the transition much easier. As discussed earlier, innerlayer alignment can still be black magic, so these changes are much slower. Here are some good starting guidelines:

1. Automatic scripting of the stackup, core type, scaling details and prepreg materials in a single pick/place Web-based tool eliminates any chances of input error due to reading of stackup data or scaling values by a CAM operator. It also allows the process engineering group to make changes that will now be updated on the next production run.

2. PEP processing is one of the least understood processes in PCB manufacturing. Optimizing all set points and understanding them will create a gate where variation is at least identified before processing. A common method for operating a PEP is to set the offset allowance values (setup and operational) at higher values than the specified tolerance. The common reason for this is that the machine will not punch each board. But isn't this the point of having a screen?

3. Watch for wear on the PEP punches and PEP punches of the wrong size. Each manufacturer has a different strategy for punching the correct size vs. board thickness. Use the recommended method even if it means having three sizes of punches.

4. Use soft tooling for drilling. Except for the optical alignment systems coming soon, nothing gives more repeatable accuracy. Hard tooling, while simple, has multiple registration steps that are reduced when using soft tooling. Be sure to change the soft tooling anytime you remove a pin. Reinserting pins defeats the reason for using soft tooling.

5. Measure drill depth on every setup. This should be done on the smallest drill size. Using an optical measuring device is the best method. Cross-section also works, but it's slow. Pin devices on 10 mil holes are a waste of time.

6. Measure every load laminated for the rate of rise (R of R). Use a wireless thermocouple with a PC interface to reduce the danger of running this test. Getting scaling data without understanding the R of R influence is like chasing a moving target.

7. Use a control depth visual measuring device to measure scale influence; do not rely on electrical circuit or x-ray systems for rounded up data. Available advanced registration systems give excellent data at the pre-drill tooling step.
TABLE 1. Key +/- 3.5 mils Innerlayer Registration Template


Front-end engineering I/L core scaling Core thickness,
completely automated construction and grain
Artwork direction
 I/L core scaling Signal/plane/mixed
 layout with facing
 prepreg type
 Film stabilization Film environment
 Plotter environment Environment temp and RH
 Plotter accuracy X/Y dimension and
 feature definition auto
 scripting of
 Film coating Film tension influence,
 or don't use
 A/W accuracy X/Y dimension and
 feature definition per
Standardized core Material stability Laminate dimensional
material stability as received
I/L Imaging and etch Imaging environment Temp and RH
include setup in each Core resist laminated Lam temperature before
evaluation temp exposure
 A/W exposure Film dimension check,
 X/Y, before setup
 A/W exposure Film exposure limits
 during HVM
 A/W exposure Film exposure limits
 life of film
 I/L image alignment Top to bottom
 Core handling. Stacking height, X/Y
 pre-DES dimension
 Post DES core Stacking height, X/Y
 handling dimension
I/L post-etch punch I/L punch target I/L target X/Y
includes setup in dimension dimension
each evaluation Punch diameter Punch hole dimension
 PEP punch accuracy Punch hole true
 position, all locations
 PEP punch alignment Punch hole to I/L
 target difference, X/Y
 PEP punch X/Y difference based on
 repeatability HVM Lot data
Oxide Core drying X/Y dimension
Lamination Caul plate bushing Bushing dimension
 Pin size Pin dimension
 Lay-up skew I/L core movement on
 pins, X/Y rotations
 Rate of rise Lam book temp vs. stack
 height and lagging
 Press cycle Total press opening/
 book ramp rate and
 delta, with procedural
 recommendations if
 Press cure Laminated book cure, Tg
 X-ray target drill Feature recognition by
 resolution lam thickness and
Include setup in each X-ray target drill Target drill hole true
evaluation accuracy position, X/Y
 X-ray target drill Target drill hole to
 alignment I/L target
 registration, X/Y
 X-ray target drill X/Y registration
 repeatability profile, based on HVM
 Lot data
 I/L scale measuring Optek/measuring feature
 data, resolution recognition by lam
 thickness /location
 I/L scale measuring Optek/measuring
 data, accuracy accuracy by lam
 thickness / location
 I/L scale measuring Measuring repeatability
 data, repeatability by lam thickness/
Drill Drill tooling pins Pin diameter
 Drill table true Spindle to table true
 position position
 Drill pinning Verification of tooling
 alignment pin Alignment / true
Include setup in each Drill run-out Dynamic spindle run-out
evaluation Drill hole true Drill feeds/speeds and
 position depth
 Drill bits Drill bit usage new,
 re-sharps, hits
 Drill pattern Validation of X/Y
 inspection locations and shape
 after drill
O/L Image O/L image O/L to drill alignment
SM Image SM image registration SM to O/L alignment

MIKE BARBETTA is a consultant with over 27 years in the industry. Previously, he has worked for Cisco Systems, PCB suppliers and chemical vendors, with experience in process engineering, technical service, engineering management and global supply management. He can be reached at JOE DICKSON is manager of the PCB SupplierTechnology Group in Hardware Reliability at Cisco Systems. He has over 30 years of PCB engineering management experience, formerly serving as director of technology for Tyco Electronics, Sigma Circuits and SBC.
COPYRIGHT 2004 UP Media Group, Inc.
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2004, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Title Annotation:Drilling
Author:Dickson, Joe
Publication:Printed Circuit Design & Manufacture
Date:Dec 1, 2004
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