Reflecting on mirrored IC pinouts: flipping the die within a package can shrink real estate and the number of vias and layers. But the chip makers will have to get on board first.

In electronics, printed circuit board design is where the proverbial rubber hits the road. A circuit board designer is constrained by many factors, some of them outside his control. The applications engineers want to cram more and more circuitry into smaller and smaller circuit boards. At the same time, clock frequencies keep going up, resulting in designs that must be more cognizant of electromagnetic compatibility issues. All of this conspires to force circuit board designs into additional layers with more and more Band-Aids to fix EMC problems, which add cost to design.

Many designs feature multiple memory ICs or multiple controller ICs boasting many pins that must be interconnected. Any designer who has been in the industry for even a short time has seen designs riddled with vias used to complete these connections. These designs usually require many layers just to fit all of these interconnections into the required overall board size.

To help solve these design problems, I am proposing that IC manufacturers produce two different versions of their ICs. One would have the pinouts exactly as they are today, and another would feature the pins mirrored.

It would be as if the chip makers had flipped the die upside-down inside the IC packaging. Refer to FIGURE 1 for a diagram of a simple 16-pin IC and how it would look in its original form and in its mirrored form.

[FIGURE 1 OMITTED]

Using mirrored parts will make these interconnections much easier. Take the simplest scenario, for example, where there are only two ICs to be interconnected--one on the top of the board and the other directly below it on the bottom side of the board. See FIGURE 2.

[FIGURE 2 OMITTED]

Here, the mirrored chip is actually mounted on the bottom side of the board and the normal chip is shown moved away from its mounting location directly on top of the mirrored part. With mirrored parts mounted directly on top of one another, interconnecting the same pins would involve fanning a via a short distance out from each pad and not require any additional routing.

As the pin count goes up, the payoff increases proportionally. Consider a 64-pin BGA, a small pin-count by today's BGA standards. With mirrored parts, the situation in FIGURE 3 is similar to that depicted in Figure 2. Here we can see that the vias needed to route out from every internal pin become an immediate conduit to connect to the corresponding pin on the mirrored part.

[FIGURE 3 OMITTED]

Or consider a row of chips, such as memory ICs, that must be connected together. FIGURE 4 shows a simplified example of what this would look like. As you can see, the connections become very straightforward with mirrored parts.

[FIGURE 4 OMITTED]

To get a sense of the magnitude of the advantages mirrored ICs can offer, a test setup was created with five 20-pin SOICs lined up side by side. Each of the pins from each IC was electrically tied to the same pin numbers from each of the other ICs. In other words, pin 1 from the first one was tied to pin 1 of the second one and to pin 1 of the third one and so on. These connections were then routed using an autorouter for a two-layer board. All of the default settings from the autorouter were accepted; the autorouter took five passes to complete the design and it placed 74 vias and had a total trace length of .1174" (2.98 mm).

Then, the second and fourth ICs were changed to mirrored versions. The autorouter was then run on that design with exactly the same setup parameters, and the result can be seen in FIGURE 5. In this case, the autorouter placed 34 vias and had a total trace length of .065" (1.65 mm). Being able to use mirrored parts resulted in a 54% reduction in vias and a 45% reduction in total trace length. In addition to that, the overall board area needed for this circuit was about 37% less with the mirrored design than with the unmirrored one.

[FIGURE 5 OMITTED]

Finally, a more realistic design was autorouted to compare the use of mirrored ICs. Four 100-pin QFPs were connected as would be typical in a memory circuit. The design was then autorouted with four different scenarios: a two-layer and a three-layer version utilizing both mirrored and unmirrored ICs. A keep-out was put under each chip to guarantee a ground plane under the die. The three-layer versions could use a fourth layer as a solid ground plane under the entire circuit. The autorouter parameters were the standard default setup. FIGURE 6 shows the two-layer design with standard pinouts. This design had 375 vias and a total trace length of 487 inches. The autorouter could not complete this design error-free.

[FIGURE 6 OMITTED]

The same design was done with two mirrored ICs. The autorouter completed it with 432 inches of trace length and 188 vias, and it was completed error-free. The layout can be seen in FIGURE 7.

[FIGURE 7 OMITTED]

Next, the design was created with three layers and no mirrored ICs. FIGURE 8 shows the design with all standard pin-out ICs. It was completed with 384 vias and 488 inches of trace length. It did not route error-free.

[FIGURE 8 OMITTED]

Finally, the three-layer design was done with two mirrored ICs as shown in FIGURE 9. It has 178 vias and a total trace length of 340 inches. As you might expect by now, the autorouter completed this design error-free.

[FIGURE 9 OMITTED]

The use of mirrored ICs is a win-win situation for PCB designers. But it's up to us to urge IC manufacturers to consider mirroring parts. Ideally, each IC will eventually be available in a normal and mirrored configuration. To be sure, the chip makers won't devote the capital necessary for mirroring their product lines unless a sustainable market can be demonstrated.

But mirrored ICs provide such measurable benefits--speeding up autorouting completion time, shortening the trace lengths between ICs (to the point that they may be able to share one decoupling capacitor), and reducing the board area and number of vias and layers--that IC manufacturers are likely to notice potential sales channels.

The mirrored IC is an idea whose time has come.

CHARLES CLARK is the manager of special products at Liberty University. He has 38 years of experience in drafting and PCB design in the military, aerospace, computer, medical and automotive industries. Clark can be reached at [e-mail].

MIRRORED ICs: Q&A with Charles Clark

Q. What product/segment of the industry is most likely to embrace the idea of mirrored pinouts and lobby for its implementation?

A. I think the memory chip market is the most likely to embrace this idea and would be the most anxious to implement it. It would represent a very significant cost savings if a memory board could be routed with fewer layers, fewer holes and, in some cases, less material (smaller boards).

Q. Since the chip makers are likely going to have to flip the silicon inside the package, won't they have to utilize two completely different packaging technologies, e.g., flip chip ball bonding for the face-down chip, and wire bonding for the face-up chip?

A. This would be one solution if the package were substrate-based (e.g., BGA). The chip makers would want to perform a cost analysis of each design to see, given the volumes and cost of implementation, which technology would make the most sense in each case.

Q. Won't chip makers need to make separate mask sets for mirrored ICs? That seems expensive, unless they see a chance to sell ICs for a range of products.

A. This would be another way to mirror a chip. Using this technique would involve adding fixed cost, but would have no impact on variable cost. This would be most appropriate if the particular chip volumes were large.

Q. Have any chip companies expressed interest in mirroring ICs?

A. One chip maker has expressed interest, but has not made a commitment to it yet. It appears that first the demand must come from the marketplace, then the supply will come from the chip manufacturers.

Q. Will this idea work with newer memory, such as DDR, and other designs with tightly length-matched busses? Won't flipping the silicon make one set of connections shorter and another set longer?

A. There can't be any shorter/tighter matched busses than

a traditional part placed on one side of the board and a mirrored part placed just opposite on the other side of the board. Granted, the connections go through vias, but this is more than compensated for by the lack of length in the connection.

Q. Doesn't the use of parts with mirrored pinouts only yield a routing advantage with a lot of redundant connections on several "like" parts?

A. The answer is an emphatic no.

Q. Do you have a patent pending? Didn't someone patent something similar years ago?

A. Liberty University does have a patent pending. We have seen patents that refer to mirroring but not in the way our patent deals with it. Our patent attorney has asked that we say no more at this time.