Rambus to Present Technical Papers and Demo RaSer Technology at DesignCon 2002.

Business Editors/High-Tech Writers

DesignCon 2002

LOS ALTOS, Calif.--(BUSINESS WIRE)--Jan. 29, 2002

Rambus Inc., the leading provider of high-bandwidth chip connection technology, will present two technical papers at this year's DesignCon in Santa Clara, California, January 28-30. The first paper describes methods for modeling Rambus' next generation 3.2GHz Yellowstone memory signaling technology. The second paper outlines a novel technique for high-speed model optimization. In addition, Rambus will for the first time demonstrate its 0.13-micron 3.2 Gigabits per second (Gbps) RaSer Quad serial link technology in the Platinum Sponsor Booth No. 503.

Interconnect Design and Modeling of a 3.2 Gbps/pair Bi-directional Differential Memory System

Session HP-10

Tuesday, January 29, 2:00pm - 2:50pm

Rambus' Yellowstone memory signaling technology implements low-swing differential signaling to achieve data rates of 3.2GHz and beyond. A low-swing differential interconnect system at a multiple-gigabit data rate using low-cost and conventional packaging and PCB technologies poses many signal-integrity challenges. High-frequency effects such as conductor/dielectric losses, trace/via coupling, impedance mismatches, and process variations must be understood to optimize voltage and timing margins of the overall system. Robust modeling and simulation methods are developed by testing several prototypes. These are measured in time and frequency domains to generate HSPICE models. 3D full-wave analyses of wirebond BGA packages are used to optimize the designs. Measured and simulated S-parameters are directly incorporated into ADS to improve simulation accuracy. Finally, arbitrary bit patterns are used to correlate the simulation results with measurements.

A Generalized Optimization Technique for Model Extraction from both TDR and VNA Measurements Extracting and Building Signal-Integrity Models

Session HP-22

Wednesday, January 30, 3:00pm - 3:50pm

This presentation discusses a general approach to extract accurate interconnect models over a wide bandwidth from time-domain-reflectometer or vector-network-analyzer measurements. It is based on an efficient optimizer that interactively calls any given circuit simulator. The models are customized to take advantage of each simulator's built-in modeling capability. For example, HSPICE's W-element-coupled transmission line models, with skin effect and dielectric loss, are extracted from such individual components as package, connector, and PCB traces. The time-domain waveform of a complex memory channel can now be easily correlated. Architectural flow and global and local iterations, piecewise-linear source models, weighting functions, and time-windowing are discussed.

First Industry Demonstration of the 0.13-micron 3.2Gbps RaSer(TM) Quad Serial Link Technology

Rambus Booth No. 503

As network equipment moves to support higher line rates and aggregate switch bandwidth, developers are integrating serializer -- deserializer ("SerDes") functions into line card and backplane traffic manager devices. Speed, reliability and power are key to enabling these next generation line cards and switch fabrics. Rambus will demonstrate the low jitter, low bit error rates, and extremely low power of the new RaSer 0.13-micron 3.2Gbps quad SerDes cell.

About Rambus Inc.

Rambus Inc. designs, develops and licenses high bandwidth chip-connection technology and provides the comprehensive engineering support necessary for a complete system solution. Rambus' technology and intellectual property are licensed to leading semiconductor suppliers including DRAM, controller and microprocessor manufacturers, ASIC developers, and foundries for use in computer, consumer and networking systems such as personal computers, workstations, servers, game consoles, set top boxes, digital HDTVs, high-speed switches and routers.

Rambus and RDRAM are registered trademark of Rambus Inc. RaSer is a trademark of Rambus Inc. Other trademarks that may be mentioned in this release are the intellectual property of their respective owners.