REPEAT/Teradyne Introduces Integra FLEX; New Universal Slot Architecture Sets a New Standard for Semiconductor Test.Business/Technology Editors
REPEATING... due to incorrect web address in the 8th graph.
BOSTON--(BUSINESS WIRE)--March 20, 2002
Teradyne introduces the next step in high-volume, high-mix IC test evolution: the Integra FLEX. A Universal Slot architecture combined with self-contained SOC Tester Per Pin(TM) instruments provide production managers with new freedom to match test capacity to device coverage needs. Spanning multi-site DFT DFT - discrete Fourier transform to standard analog to SOC, Integra FLEX will change the way IC makers and subcontract test companies think about the mix of equipment they need on their test floors.
Independent Time Tracks(TM) per instrument and Background DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive processing boost efficiency, giving FLEX high site count concurrent test capability. Multi-level IG-XL5 software helps test engineers get products to market sooner by combining low level tester control with a template authoring environment. Already in use by lead customers, Integra FLEX will be demonstrated April 16-18 at the industry tradeshow Semicon Europa in Munich, Germany.
"High-volume, high-mix device manufacturing has changed production test," said Mark Jagiela, Teradyne Vice President and General Manager, Semiconductor Test Business Group. "IC manufacturers and subcontract test companies want fewer tester types and wider device coverage. Integra FLEX meets these needs, and adds a new element of configuration freedom. FLEX also provides increased test capacity through multi-site concurrent test," Jagiela concludes, "Fewer tester types, wider device coverage, and fewer testers. That's what the FLEX is all about."
Tester Array Architecture
Unlike conventional testers with centralized cen·tral·ize
v. cen·tral·ized, cen·tral·iz·ing, cen·tral·iz·es
1. To draw into or toward a center; consolidate.
2. clocks and restricted instrument arrangements, Integra FLEX is more a `tester array'. Universal slots allow users to target FLEX for today's device plan, knowing that they can reconfigure the system easily when those needs change. Each instrument module is independent, with local clock, sequencer See MIDI sequencer.
(music) sequencer - Any system for recording and/or playback of music via a programmable memory which stores music not as audio data, but as some representation of notes. , and dynamic setup. Parallel DC-to-microwave analog, high density CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. differential digital, scan and memory test features all reside in Integra FLEX's air cooled test head. FLEX offers wide device coverage and lower capital cost.
Integra FLEX multi-level IG-XL5 gives test engineering, for the first time, the ability to mix fully graphic template programming, high level test procedures, and low level precise control. This software promotes portable test IP without the overhead of repeated setup commands of conventional systems. With the ability to go from single-site test to multi-site test Multi-site test, or "multisite test", or "concurrent test", or "parallel test" are all semiconductor Automatic Test Equipment (ATE) terms that generally refer to testing of multiple "devices" at the same time. quickly, FLEX supports fast production volume ramps.
More Parallelism An overlapping of processing, input/output (I/O) or both.
1. parallelism - parallel processing.
2. (parallel) parallelism - The maximum number of independent subtasks in a given task at a given point in its execution. E.g. , Higher Throughput
The independent instrument Time Tracks(TM) architecture provides multiple clock and sequencers per DUT DUT Dutch (language)
DUT Device Under Test
DUT Diplôme Universitaire de Technologie (French University Graduation in Technology)
DUT Dalian University of Technology (also seen as DLUT) socket. By increasing the number of separate time domains from a few to dozens, FLEX changes the way you approach parallel test. More sites and more IP cores can be tested at once, a step function improvement in test economics.
When testing mixed signal, linear, or doing memory redundancy analysis, Integra FLEX moves and processes data in the background, in parallel with testing. This background DSP avoids the 20-50% or more test time overhead seen on test systems with serial or in-line DSP structures. Integra FLEX boosts site count for DSP intensive testing with a special purpose multi-processor computing core in addition to the user computer.
Price and Delivery
Integra FLEX test systems are shipping today and volume shipments will begin in Q3 2002. Pricing for the Integra FLEX varies by configuration starting around $500,000. To learn more about Integra FLEX, visit www.teradyne.com/integraflex.
Teradyne (NYSE NYSE
See: New York Stock Exchange : TER Third version. See bis. ) is the world's largest supplier of automatic test equipment and is also a leading supplier of high performance interconnection systems. Teradyne's test products are used by manufacturers of semiconductors, circuit assemblies, voice and broadband telephone See IP phone, softphone and VoIP. networks. Teradyne's backplane An interconnecting device that has sockets for printed circuit boards to plug into.
Passive and Active
Although resistors may be used, a "passive" backplane adds no processing in the circuit. assemblies and high-density connectors are used by manufacturers of communications and computing systems central to building networking infrastructure. The company had sales of $1.4 billion in 2001 and currently employs about 8000 people worldwide. For more information visit www.teradyne.com.
Time Tracks and SOC Tester Per Pin are trademarks of Teradyne.