REMINDER/SynTest Exhibits and Hosts Press Conference At DATE Conference in Paris, France Next Week.News Desks/High Tech Writers REMINDER...for March 28 - 30 (Tues.-Thurs.) DATE Conference, Booth No. 114 --(BUSINESS WIRE)
WHO: SynTest Technologies, Inc. (Sunnyvale, CA, USA), a supplier of
DFT tools for IC designers and foundries
WHAT: SynTest is exhibiting at booth number 114 and hosting a press
conference addressing its presence in Europe and VHDL focus.
WHEN:
Exhibit
Tuesday, Wednesday and Thursday, March 28 through 30, 2000, at the
DATE conference, Booth No. 114, Palais de Congres, Paris, France
Press Conference
Tuesday, March 28,2000, 2:30p.m. Room 221M, Palais de Congres
Please RSVP to Georgia Marszalek, 650 345 7477, georgia@valleypr.com
Additional Information If you would like to schedule an appointment to meet with SynTest at the DATE Conference, please contact Jon Turino, European Business Manager, 503/452-4610, jon@syntest. SynTest Technologies, Inc. was founded in 1990 and is headquartered in Sunnyvale, CA, USA. The company develops and markets DFT DFT - discrete Fourier transform , logic and memory BIST BIST - Built-in Self Test synthesis, boundary scan See scan technology. boundary scan - The use of scan registers to capture state from device input and output pins. IEEE Standard 1149.1-1990 describes the international standard implementation (sometimes called JTAG after the Joint Test Action Group which began the , ATPG ATPG Automatic Test Pattern Generation ATPG Automatic Test Program Generator and fault simulation software tools and offers consulting services throughout the world to semiconductor companies, ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. designers and test groups. SynTest's products include TurboBIST (TM), a memory BIST suite; TurboBSD(TM), a boundary-scan test suite; TurboCheck(TM), a gate-level and RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; design and testability analyzer for Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. ; TurboFault(TM), a fast fault simulator; and TurboScan(TM), a full-scan and partial-scan synthesis and ATPG program. Visit www.syntest.com for more information about SynTest. Visit www.date-conference.com for information about the DATE Conference Press Contact: Georgia Marszalek, ValleyPR for SynTest, 650-345-7477, georgia@valleypr.com. Note to Editors: TurboBIST, TurboBSD, TurboCheck, TurboFault and TurboScan are trademarks of SynTest Technologies, Inc. All other trademarks are the property of their respective owners. |
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