REMINDER/Monterey Design Systems-sponsored panel asks: Has the ``No Economy'' Killed IC Design?; Panel of Industry CEOs will Discuss Benefits and Challenges of COT Design.Business Editors/High-Tech Writers REMINDER...for Thursday (Nov. 21) SUNNYVALE, Calif.--(BUSINESS WIRE)--Nov. 14, 2002 Monterey Design Systems is sponsoring a panel composed of electronics industry leaders to discuss the "No Economy" -- the deadlocked economic and engineering constraints that are currently gripping the semiconductor industry. In the keynote address keynote address n. An opening address, as at a political convention, that outlines the issues to be considered. Also called keynote speech. Noun 1. , Jacques Benkoski, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of Monterey, will outline the salient characteristics of the "No Economy" and set the stage for the panelists to present their views on the current environment and its long-term impact on IC design. Technological innovation is outpacing our ability to fully implement and reap the benefits of that innovation. The pace of advancement has accelerated to the point where many new technologies become obsolete before they have a chance to reach critical mass. Today's engineers are faced with the challenges posed by increasingly complex nanometer process technologies, shorter and more volatile market windows, and cutbacks in engineering budgets. Customer-Owned Tooling (COT) design is one of the answers often proposed. COT offers the benefits of improved circuit performance, faster turnaround time (1) In batch processing, the time it takes to receive finished reports after submission of documents or files for processing. In an online environment, turnaround time is the same as response time. , and lower engineering and production costs. However, COT design does not come without risk. The panel will include a discussion of the benefits, challenges, and tradeoffs of adopting in-house COT physical design flows. When: Thursday, November 21, 2002. Registration begins at 4:00 pm. The event will begin at 4:30 pm, followed by a Q&A discussion. Refreshments will be served. Where: Westin Hotel, Santa Clara, California Santa Clara, California (IPA: /ˌsæntəˈklærə/) , founded in 1777 and incorporated in 1852, is a city in Santa Clara County, in the U.S. state of California. Format Keynote presenter: Jacques Benkoski, president and CEO, Monterey Design Systems Panelists: Mark Templeton, president and CEO, Artisan Components Jack Harding, chairman, president and CEO, eSilicon John Bourgoin, chairman and CEO, MIPS Technologies Yoav Nissan-Cohen, co-CEO, Tower Semiconductor Levy Gerzberg, president and CEO, Zoran Moderator: Erach Desai, electronics analyst, American Technology Research To register for the panel, please visit the Monterey Design Systems website events page at http://www.montereydesign.com/newsevents/CEO_COT_panel.htm. About Monterey Design Systems: Monterey Design Systems provides electronic design automation software that enables integrated circuit designers to take their circuits from completed logic design to manufacturing ready output. Built to handle the most demanding semiconductor process requirements, the company's products -- IC Wizard(TM) hierarchical design planner, Sonar(TM) physical prototyper, and Dolphin(R) physical implementation system -- combine to provide the most streamlined physical design flow on the market. Monterey Design Systems is privately held and partners with other leading EDA companies, such as Cadence (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. - News) and Synopsys (Nasdaq:SNPS SNPS Space Nuclear Power System - News), to ensure interoperability in all existing design flows. Key customers include LSI LSI: see integrated circuit. (Large Scale Integration) Between 3,000 and 100,000 transistors on a chip. See SSI, MSI, VLSI and ULSI. Logic, STMicroelectronics, Fujitsu Ltd., Flextronics Semiconductor, and NEC (NEC Corporation, Tokyo, www.nec.com, www.necus.com) An electronics conglomerate known in the U.S. for its monitors. In Japan, it had the lion's share of the PC market until the late 1990s (see PC 98). NEC was founded in Tokyo in 1899 as Nippon Electric Company, Ltd. Electronics. Monterey Design Systems is located at 894 Ross Drive, Sunnyvale, CA 94089-1443, tel: 408/747-7370, fax: 408/747-7377, http://www.montereydesign.com. |
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