REMINDER/@HDL to Exhibit at International System-on-Chip Conference.Business Editors/High-Tech Writers REMINDER...for Monday (April 19) 1st International System-on-Chip (SoC) Conference NEWPORT BEACH Newport Beach, residential and resort city (1990 pop. 66,643), Orange co., S Calif., on Newport Bay and the Pacific Ocean; inc. 1906. It is a popular seaside resort and yachting center. Manufactures include electrical and medical equipment, computers, boats, and adhesives. , Calif.--(BUSINESS WIRE)--April 19, 2004 @HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. , Incorporated
WHO: @HDL, Incorporated, a leading supplier of electronic design
automation software for the functional verification of complex
semiconductor devices.
WHAT: You are invited to attend the 1st International
System-on-Chip (SoC) Conference, taking place at the Radisson
Hotel, Newport Beach, California. @HDL will be exhibiting at the
conference, presenting technical details of our @Verifier and
@Designer-PRO products families.
Come see why @HDL has emerged as the technology leader in
advanced, assertion-based functional verification, delivering PSL
and SystemVerilog products to significantly improve the
productivity of SoC and ASIC design teams. Find more bugs faster
in your RTL development -- with automatic model checking,
extensive multiple clock domain verification/analysis and tight
integration with simulation.
WHEN: The International SoC Conference is being held Monday and
Tuesday, April 19-20, 2004. @HDL will be participating in the SoC
Exhibits, running from 5:30 p.m. through 8 p.m. on Monday, April
19.
PRESENTATION DETAILS: The @Verifier family is the industry's most
comprehensive assertion-based verification product available
today, with support for both PSL and SystemVerilog. The family
includes @Verifier-DP for distributed processing on existing
simulation server farms and @Verifier-ZX, adding the powerful
formal solvers based on the IBM RuleBase technology. @Verifier
helps designers and verification engineers to quickly find bugs
earlier in the design cycle by incorporating some of the latest
advancements in technologies ranging from formal solver
algorithms, to design and space reduction techniques, and
extensive support for multiple clock domain verification and
analysis.
An industry first, @Designer-PRO delivers a complete solution for
expressing, visualizing, debugging, verifying and leveraging
assertions. Included in the product is the patent-pending @HDL
Assertion Studio(TM) technology; to provide the link between the
difficulty of learning assertion languages and the need for
high-quality assertions to speed up the RTL functional
verification process.
WHERE: More information about the International SOC Conference can
be found on the @HDL website, www.atHDL.com.
About @HDL: @HDL is an electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) company focused on accelerating functional verification of SoC and silicon IP designs. The @Verifier, @Verifier-DP, @Verifier-ZX, @Designer and @Designer-PRO products deliver significant verification productivity improvement, through system-level design analysis and debugging, automatic formal model checking, and tight integration with existing RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; simulation environments. Supporting both the Accellera PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. and SystemVerilog assertion languages, @HDL delivers an effective assertion-based verification product suite to its customers, including such companies as AMD (Advanced Micro Devices, Inc., Sunnyvale, CA, www.amd.com) A major manufacturer of semiconductor devices including x86-compatible CPUs, embedded processors, flash memories, programmable logic devices and networking chips. , Cisco, Fujitsu, OKI Semiconductor, SiNett, Raza Microelectronics, Renesas and Toshiba. @HDL is a member of the Cadence (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ) Connections Program, the Mentor Graphics (Nasdaq:MENT) Value Added Value Added The enhancement a company gives its product or service before offering the product to customers. Notes: This can either increase the products price or value. Partners program and the Synopsys (Nasdaq:SNPS SNPS Space Nuclear Power System ) in-Sync Program. For more information, call 408-433-9997, visit www.atHDL.com or email to info@atHDL.com. @Verifier, @Verifier-DP, @Verifier-ZX, @Designer, @Designer-PRO and Assertion Studio are trademarks of @HDL. All other trademarks or registered trademarks mentioned in this release are the property of their respective owners. |
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