RAID-on-a-chip [ROC] processors change the storage equation: Part 1.

As storage environments continue to grow and expand, systems administrators are increasingly facing the problem of having to balance their capacity and performance requirements while keeping costs in line. One of the major considerations in planning an expansion is the increased burden to the RAID storage infrastructure. These escalating demands are forcing the RAID manufacturers to take a hard look at how RAID systems are constructed and what can be done to both lower the cost and reduce the management overhead placed upon their customers.

Three things have happened that will allow for a major shift in the architecture of these machines:

* RAID technology is now well understood, as are most of the standard processes within a RAID controller such as cache coherency, read and write processes, RAID set rebuilds, volume management, mirroring, and snapshot.

* RAID systems have become pervasive for data storage.

* Significant progress has been made in emulating and embedding application-specific tasks into silicon chip technology.

[FIGURE 1 OMITTED]

This allows for a major shift in the architecture and design of RAID systems, and will create a new paradigm for both performance and cost. This inevitability has resulted in the next-generation RAID controller technology, where primary RAID functions will be embedded in silicon--resetting the performance vs. cost equation.

Traditional Storage Architectures

RAID controllers for storage systems have been in existence since the late 1980s, and are a combination of hardware and software. While processor and memory speeds have increased, the fundamental architecture of these controllers has remained unchanged. They are typically designed around a general-purpose microprocessor, which executes software instructions and is supported by discrete, task-specific ASICS, such as protocol devices and XOR/data path controllers, all of which are interconnected via a shared bus. Until recently, this traditional design has kept pace with industry needs. However, increased demands on storage systems created by content-rich applications, the expanding volume of transactions, and the migration to higher link speeds have created compute and data path requirements that architectures centered on general purpose microprocessors can no longer meet.

Modern storage systems must address the performance demands of multiple servers. Each server's data operation requires the storage system to cycle through numerous discrete steps in order to read or write data to and from disk drives. In a storage system built from general-purpose microprocessors, each step is performed sequentially and requires an interrupt service routine to be invoked. Each interrupt service routine adds latency to the system and reduces system performance.

These servicing interrupts can have a significant impact on the performance of a storage system. For example, a cache read operation requires only a single interrupt to process, and performance in the range of 18,000 to 40,000 IOPS per port is typically achieved. Reads to disk require multiple interrupts, and the data processing capability drops to between 2,000 and 6,000 IOPS per port. Finally, microprocessors processing RAID-5 require numerous additional interrupts, and only achieve between 500 and 1,000 IOPS per port. When compared with the current 15K-RPM disk drives that are capable of up to 300 IOPS per drive, the limitations of the current architectures become obvious.

The data path demands of a storage system are additionally taxed by the demands of RAID parity generation for RAID-5 and RAID-6, and by computing data integrity checksums. For instance, a single data port delivering 200MB/s of RAID-5 writes can consume in excess of 2.4GB/s of buffer bandwidth. The memory system quickly bottlenecks when it is required to concurrently support multiple storage data paths and the microprocessor's own code and data.

To further complicate matters, disk drive manufacturers are constantly developing higher capacity drives. In a RAID-5 set, there is a minimum of 3 drives, meaning 1.5TB of data. If a drive is lost, that data needs to be rebuilt, and current controllers can take days to accomplish such a large task. In addition, during the rebuild, the storage system runs in a degraded mode (i.e., using algorithms to rebuild data), affecting performance and increasing the risk of a secondary failure or total loss of data. Thus, mitigating exposure time for possible secondary disk failure is of paramount importance.

As system capacities grow and RAID systems are expanded to include SATA and SAS drives, the storage system's data path requirements will be increasingly strained. In-band data integrity checks and RAID functionality will no longer be a luxury, but a necessity for future storage systems.

RAID Storage Processors

Specialized "storage processors" are the logical solution for the data path portion of networked storage designs. This new breed of dedicated storage processors eliminates the fundamental bottlenecks associated with a general-purpose micro-processor and the shared bus architecture. RAID Storage Processors, otherwise known as RAID-on-Chip (ROC), not only provide an efficient, fully-integrated, high-speed data path, but also offload external processors by migrating deterministic storage algorithms into hardware--which is inherently better suited for performing real-time functions such as event and data synchronization.

The RAID Storage Processor is responsible for a storage-specific task called "command termination and redirection." Command termination means the RAID Storage Processor acts as a virtual target, literally intercepting the read and write commands. The processor then creates one or more new commands based on the real command that was terminated. Additional processing on each command can include host/LUN permissions checking, mapping of virtual volumes to physical disk drives, parity calculations or RAID rebuild. In addition to command termination and RAID functionality, the RAID Storage Processor is capable of intelligent cache management. The cache is implemented in fast memory at the virtual volume level, and the RAID Storage Processor then uses its virtual initiator capability to populate the cache with data that is statistically most likely to be requested by the host.

Part 2 of this article will appear in the next edition of CTR.

John Howarth is senior director of product marketing and Tim Piper is director of product marketing at Xyratex International (San Jose, CA)

www.xyratex.com