Quickturn Boosts Simulation Performance, Broadens Application of Its Cycle-based Verification Product Family.

SAN JOSE , Calif.--(BUSINESS WIRE)--Nov. 2, 1998--

SpeedSim(tm) 3.0 Performs 70 Percent Faster than

Previous Release and Doubles Useable Clock Domains for

Graphics and Communications Chip Designs

Quickturn Design Systems, Inc. (Nasdaq:QKTN) today introduced SpeedSim 3.0, the latest release of its industry-leading cycle-based simulator (CBS). Quickturn has made major architectural modifications in SpeedSim 3.0 to significantly improve the performance and expand the appeal of CBS to new users creating complex chip designs. SpeedSim 3.0 includes a new multiple clock domain (MCD) feature that enables graphics and communications chip designers to use cycle-based simulation with greater ease. It also offers a new toggle capability that allows users to test every node for state changes and grade testbenches to ensure 100 percent coverage on their designs.

"We're continuing to broaden the scope and advance the capabilities of SpeedSim," said Don McInnis, senior vice president, Advanced Simulation Division at Quickturn. "SpeedSim has routinely provided better run-times than other simulators on processor-type designs. Now, we've extended SpeedSim's performance and clock handling capabilities so that graphics and communications IC designers can experience the same benefits. In addition, we've made SpeedSim easier to use and integrate into a complete CBS verification flow. SpeedSim is an important part of our product suite for cycle-based verification (CBV) along with CoBALT(tm) and StyleCheck(tm). This CBV methodology is ideal for handling verification of high-end designs."

Quickturn has spent considerable effort enhancing the SpeedSim architecture to optimize compile and run times for large Verilog designs up to eight million logic gates. Users will experience an overall increase in compile and run time performance based on the mix of decoder, I/O, and memory addressing constructs in their designs. For example, decoder construct compile and run times increase by 50X and 3.2X respectively.

Quickturn has enhanced SpeedSim's Simultaneous Test (ST) simulation capability and symmetric multiprocessing (SMP) support resulting in performance improvements of up to 70 percent over the previous product release. Unlike other commercial simulators, SpeedSim 3.0 enables designers to run up to 32 tests simultaneously on a single CPU to increase simulation throughput. SpeedSim 3.0 also adds SMP support for Hewlett-Packard workstations, in addition to Sun servers.

For graphics and communications chip designers, Quickturn has quadrupled the number of interacting clock domains from four to 16 while improving compile and run time simulation performance. Quickturn re-wrote SpeedSim's clock handling routines to accommodate the diverse clocking schemes now utilized in large ASIC designs based on SOC (system-on-chip) architectures.

Ease-of-Use and Co-Verification

In addition to increased performance and multiple-clock domain support, Quickturn has significantly enhanced SpeedSim's ease of use and co-verification capabilities. SpeedSim 3.0 includes a user interface to the popular Tcl scripting language that allows fast set up in large organizations where new SpeedSim users need to start their simulation projects quickly. The Tcl interface also gives Quickturn users a common front-end to emulation and simulation through an industry-standard scripting language that eases integration in complex regression testing environments.

For developers of embedded processor systems who need rapid prototyping capability, SpeedSim 3.0 features a hardware/software co-simulation interface to Synopsys' Eaglei(tm) tool. The interface allows software programmers to run and debug their code on Eagle while the hardware design is simulating on SpeedSim. SpeedSim 3.0 also includes Q/Link(tm) --Quickturn's co-simulation interface to emulation systems. Now chip designers can start debugging their hardware models with SpeedSim and easily move their complete design environment to the emulator for even faster verification all the way to in-circuit speeds.

Pricing and Availability

SpeedSim 3.0 is available immediately with U.S. list price starting at $45,000. The ST version has support for 32 parallel simulation with U.S. list price at $85,000. SpeedSim 3.0 is available in the following platforms: Solaris, HP/UX, IBM AIX, Windows NT and Linux.

Quickturn Design Systems, Inc. (Nasdaq:QKTN) is the leading provider of verification products and time-to-market engineering (TtME) services for the design of complex ICs and electronic systems. The company's verification solutions are used worldwide by developers of high-performance computing, multimedia, graphics and communications systems. Quickturn is headquartered at 55 W. Trimble Road, San Jose, CA 95131-1013; Telephone: [phone]. For more information, visit the Quickturn Website at www.quickturn.com or send e-mail to [e-mail].

Quickturn, the Quickturn logo, SpeedSim, Q/Bridge, Q/Link , CoBALT, StyleCheck, and TtME are registered trademarks or trademarks of Quickturn Design Systems, Inc. Eaglei is a trademark of Synopsys Corporation.