QuickLogic Announces QuickDSP Family for High-Performance DSP Applications.

Business Editors &High-Tech Writers

SUNNYVALE, Calif.--(BUSINESS WIRE)--Jan. 24, 2000

     --   Fully Integrated, Dedicated DSP Hardware With RAM and
          Programmable Logic
     --   Up to Four Times Faster Than Other Solutions
     --   Complete Software Support Enables Quick Development of DSP
          Functions

QuickLogic Corp. (Nasdaq:QUIK), a pioneer of ESP (embedded standard products) technology, today announced the QuickDSP(TM) family of ESPs, a unique combination of embedded DSP performance and programmable logic flexibility for a wide range of real-time DSP applications.

Devices in QuickLogic's newest ESP family perform up to four times faster than traditional programmable logic solutions for functions such as floating point arithmetic, FIR and IIR filters, color space conversion and FFTs. Combined with QuickDSP software, the new family provides experienced DSP designers with a level of performance previously unavailable and new DSP designers with a fast and easy way to implement a wide range of standard DSP functions.

&uot;A large number of design engineers have turned to programmable logic devices as hardware alternatives or supplements to DSP processors,&uot; said Chuck Tralka, director of strategic marketing for QuickLogic. &uot;While traditional programmable logic architectures have difficulty supporting the arithmetic logic inherent in DSP applications, the QuickDSP family offers embedded computational units specifically designed for flexible, high performance arithmetic functions.&uot;

Embedded Performance and Programmable Flexibility

The QuickDSP devices include up to 18 Embedded Computational Units (ECUs) with dedicated 16-bit adders and registers and 8-bit multipliers. Each ECU is connected to the programmable logic array as well as the RAM block array, permitting data to flow between all three sections of the device.

A three-bit instruction set, sequenced from the logic array, memory, or external pins, dynamically configures each ECU for any of eight possible operations including: registered or flow-through multiply, add, multiply-add, or multiply-accumulate.

&uot;Because input data to the ECUs can come from any source in the device, it can be changed dynamically -- enabling variable-coefficient DSP applications,&uot; said Bill Smithson, vice president of engineering for QuickLogic. &uot;This flexibility allows the designer to realize complex single or multi-sampling algorithms using single or multiple data paths.&uot;

QuickDSP family members support single clock-cycle, 8-to 32-bit arithmetic functions with no pipelining, including up to 220 MHz multiplies and 394 MHz adds. From 46K to 82K bits of dual-port RAM provide high speed FIFOs, program instruction, and data memory.

With a maximum of 662,200 system gates, the four QuickDSP devices address the majority of DSP applications including image processing, video color space conversion, voice echo cancellation, audio signal processing, and forward error correction (FEC) functions. Examples of potential end-user markets include HDTV, wireless communications and digital subscriber line (DSL) systems.

Table 1:  QuickDSP Device Family

Device      Max System Gates      No. ECUs(a)    RAM Bits      Max I/O
QL7100      292,160               10             46,080        256
QL7120      373,440               12             55,296        320
QL7160      558,464               16             73,728        448
QL7180      662,208               18             82,944        512
(a) ECUs = Embedded Computational Units

Software Enables Fast, Accurate Designs

QuickDSP software enables both DSP experts, and those designers working with DSP as part of a broader design, to quickly and easily create highly differentiated products and get them to market faster than ever. With just a few clicks of a mouse, the integrated DSP Wizard creates optimized functions such as fixed and floating-point arithmetic logic as well as FIR and IIR filters.

The QuickFILTER(TM) application automatically generates filter coefficients, and allows quick and easy FIR/FFT response analysis and system simulations.

Pricing and Availability

Pricing for the QuickDSP family starts at $19.95 for the QL7100 in 50,000 piece quantities. The first member of the QuickDSP family, the QL7180, and accompanying QuickDSP software, are expected to be available in Q2'00. The remainder of the QuickDSP family is expected to be available in Q3'00.

Safe Harbor Statement

This news release contains forward-looking statements based on current expectations that involve risks and uncertainties. QuickLogic's actual results may differ from the results described in the forward-looking statements. Factors that could cause actual results to differ include, but are not limited to, general conditions in the semiconductor industry, interest rate fluctuations, and the impact of competitive products. These and other risk factors are detailed in QuickLogic's periodic reports and registration statements filed with the Securities and Exchange Commission.

About QuickLogic

QuickLogic Corp. began developing the Embedded Standard Product (ESP) architecture in 1998, an innovation on our core Field Programmable Gate Array (FPGA) technology, that delivers the guaranteed performance and lower cost of standard semiconductor products and the flexibility and time-to-market benefits of programmable logic.

QuickLogic's ViaLink(R) metal-to-metal interconnect technology offers high performance and is the foundation of the company's ESP families as well as our core FPGA products. Founded in 1988 by the inventors of the PAL(R), the company is located at 1277 Orleans Dr., Sunnyvale, Calif., 94089-1138. For more information please visit the QuickLogic web site at www.quicklogic.com

Note to Editors: The QuickLogic name and logo are registered trademarks and QuickDSP and QuickFILTER are trademarks of QuickLogic Corporation. All other brands or trademarks are the property of their respective holders and should be treated as such.