Qualis Releases SPI 4.2 Verification Component for Verisity Specman Elite.

Business Editors/High-Tech Writers

LAKE OSWEGO, Ore.--(BUSINESS WIRE)--Feb. 25, 2002

Verification Component for Specman Elite Reduces

Time-to-First-Test 10-25x by Merging Protocol-specific

Knowledge With Advanced Verification Methods

Qualis Design Corporation, the independent leader in advanced verification methodologies, announces the availability of a powerful new Verification Component that supports the SPI level 4 phase 2 protocol specification for the Verisity (Nasdaq:VRST) Specman Elite(TM) simulation platform. Based upon Qualis' advanced plug-and-play Domain Verification Component(TM) (DVC(TM)) architecture, the new component allows verification engineers to quickly build complex networking verification environments that leverage the power of Specman Elite and advanced verification methodologies. The new SPI 4.2 component is Qualis' latest addition to its rapidly expanding family of networking DVCs for the Specman and VERA testbench simulators.

"The new SPI 4.2 Domain Verification Component joins our SONET, Utopia, ATM and Ethernet DVCs as a powerful new platform for verifying protocol-centric designs," says Michael Horne, president and CEO of Qualis. "Verification engineers can quickly assemble complex verification environments for their networking designs and begin writing useful testbenches within hours of installing our DVCs, saving months of effort they would otherwise spend creating and debugging the test environment. No other solution gives this magnitude of verification productivity."

The SPI 4.2 DVC was developed in accordance with the Optical Internetworking Forum specification OIF-SPI4-02.0 to provide a complete protocol test environment, which supports random and directed stimulus generation, automated response checking and functional coverage. The DVC provides a constrainable interface for the generation of packets over multiple channels, detects protocol violations and checks for compliancy to the OIF specification. The SPI 4.2 DVC can be used in conjunction with the Qualis ATM DVC to support higher layer traffic generation.

Qualis DVCs for Specman Elite leverage the power of Verisity's popular testbench simulator. As a charter member of Verisity's Verification Alliance(TM) partner program, Qualis recognizes the role of Specman Elite as one of the true "Verification Operating Systems" of the future. Through collaboration with Verisity, the new DVCs for Specman Elite will continue to support the latest enhancements to the e(TM) language and simulator, ensuring that engineers can count on full DVC compatibility, interoperability and performance.

Simulation technology that delivers results

The SPI 4.2 DVC is much more than an interface simulation model. The new technology embeds protocol knowledge and advanced verification techniques in an easy-to-use reusable block. The SPI 4.2 DVC dramatically raises the level of productivity of verification engineers by providing a pre-verified OIF-SPI4-02.0 compliant stimulus generation and automated response checking component that saves the time otherwise spent architecting, writing, debugging and maintaining a Specman test environment. Verification engineers can quickly assemble a multi-protocol verification environment for complex datacom designs and immediately focus on their primary goal: writing testbenches that verify their design.

"With years of experience helping our networking customers verify their leading-edge designs, we have developed a highly reusable verification component technology that truly delivers a 10x to 25x improvement in verification productivity," says Janick Bergeron, chief technology officer at Qualis. "With the help of our DVCs and our patent-pending interconnect technology, verification engineers using Specman can now jump immediately to writing testcases for their design. And with Qualis' expanding library of DVCs, engineers are able to quickly build multi-protocol environments for complex applications like routers, framers and network processors."

The new SPI 4.2 Domain Verification Component offers a rich set of features, including:

-- SPI level 4 phase 2 comprehensive test environment compliant to
OIF-SPI4-02.0. Configurable for verifying a system with multiple channels of
arbitrary traffic

-- Leverages the full power of the Specman Elite simulation engine. Full
support of SoC/ASIC, FPGA, system and board-level verification

-- Full support of automatic random, constrained random and directed testcase
creation

-- Built-in flexible checking mechanism, with on-the-fly protocol
checkers/monitors and coverage support

-- Extendable architecture allows user to create standalone test environment or
embed the DVC in a larger existing test environment

-- Compatible with the ATM DVC for creation of higher layer packets

-- Full support for DIP-2 & DIP-4 generation, checking and corruption

-- Supports LDVS I/O on data interface, LVTTL I/O on FIFO status and LVDS I/O
on FIFO status

-- Support of calendaring, narrow mode operation and hitless bandwidth
reprovisioning

-- Provides in-band address, start/end of packet indication and start-of-FIFO
status indication

For a complete listing of features of the SPI 4.2 DVC for Specman, visit our Web site at http://www.qualis.com/dvc.spi4.2.specman.pdf.

Pricing and availability

The SPI 4.2 DVC is available today for the Verisity Specman Elite platform and supports interfacing to Verilog and VHDL designs. Annual licenses are priced at US $10,000, with volume discounts available for customers who run large regression simulations. The SPI 4.2 DVC for Specman comes with full documentation and example configurations for typical SPI 4.2 verification environments. Qualis also offers full methodology training and support services for its DVCs, including its QuickRamp(TM) family of DVC deployment solutions. For more information, visit http://www.qualis.com/dvc.html.

About Qualis Design

Qualis Design is the leading independent verification methodology company offering a rich selection of productivity-enhancing Domain Verification Components(TM), methodology consulting, and best-in-class training services. By leveraging its deep experience in verifying networking, processor/SoC and wireless products, Qualis creates verification product solutions that solve the most challenging functional verification problems in the world. Users of Qualis revolutionary technology and verification methodology know-how build sustainable competitive advantages that keep them on the edge. Qualis is headquartered in Lake Oswego, Ore., and has development centers in Ottawa, Ontario; and Grenoble, France. To learn more, visit http://www.qualis.com/.

Note to Editors: Qualis and the Qualis logo are registered trademarks of Qualis Design Corp. DVC, Domain Verification Component and QuickRamp are trademarks of Qualis Design Corporation. Specman Elite and 'e' are trademarks of Verisity Design, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.