Qualis Breaks the Verification Bottleneck with Powerful Family of Domain Verification Components.

Business Editors/Technology Writers

LAKE OSWEGO, Ore.--(BUSINESS WIRE)--Feb. 25, 2002

New Verification Components Supporting VERA(R) and Specman Elite(TM)

Testbench Tools Give Engineers Access to Unparalleled Verification

Productivity With Language Independence

Qualis Design Corporation, the independent leader in advanced verification methodologies, announces the release of powerful Domain Verification Components for verifying complex SoC/ASICs, FPGAs and systems for networking, wireless and core interconnect. Based upon a novel and powerful plug-and-play technology, the Qualis Domain Verification Component(TM) (DVC(TM)) technology promises to deliver a 10x to 25x productivity improvement over traditional Verilog- and VHDL-based verification methods. With DVCs, verification engineers can now reduce the time it takes to build complex verification environments for their domain-specific designs from months to just days. Qualis has announced the immediate availability of SONET, ATM, Utopia 1 and 2, SPI 4.2, and Ethernet DVCs for its networking DVC family, and is developing additional networking, wireless and core interconnect DVCs for release in 2002.

The new DVCs run as an application layer on top of Synopsys Inc.'s VERA and Verisity's Specman Elite by leveraging the powerful verification capabilities of these testbench tools. By welding together domain-specific protocol and interface knowledge with advanced, random-based verification methodologies, DVCs offer a dramatic reduction in the time it takes to test and debug complex designs. With DVCs, engineers spend their valuable time writing and running powerful testbenches instead of learning, architecting, writing and debugging complex functional verification environments. A technology brief describing the new Domain Verification Component technology can be found on the Qualis Web site at http://www.qualis.com/dvc.whitepaper.pdf.

"After years of working with networking, processor and wireless design teams at industry leading companies, we've developed a verification methodology that works exceptionally well for protocol-based designs," said Janick Bergeron, chief technology officer at Qualis and principal architect of the new technology. "We designed the DVC architecture to leverage the intrinsic power of the Specman Elite and VERA testbench tools in a language-independent way. Each DVC in the platform merges protocol- and interface-specific knowledge with our advanced verification methodology, allowing engineers to instantly extract 'expert level' productivity from VERA and Specman. And with the plug-and-play interconnect technology, even engineers with little HVL or protocol knowledge can quickly build powerful verification environments."

Mr. Bergeron is recognized as an industry expert in verification methodologies, is the author of the industry verification reference "Writing Testbenches: Functional Verification of HDL Models," and is the moderator of the popular email newsletter "Verification Guild."

A Huge Jump in Verification Productivity

Functional verification of complex SoC/ASICs, FPGAs and systems has not kept up with the huge productivity improvement in recent years from design reuse and physical synthesis technologies. Verification is now the dominant part of pre-silicon activity and has become the bottleneck in chip and system design. A huge jump in verification productivity is required to keep pace with design.

"Verification reuse through domain-specific verification component technology is finally coming of age," said Dr. William Lattin, former CEO of Logic Modeling and respected EDA industry veteran. "Verification teams can now leverage the power of verification components to manage the explosion in system verification complexity."

DVCs tackle the verification problem by addressing the three critical challenges of modern functional verification: protocol-specific stimulus generation, automated response checking, and test coverage metrics extraction. The DVC test stimulus generation blocks conform to industry standard protocols and interfaces and allow full random, constrained random, and directed test generation. Similarly, the response checking blocks support standard protocols and interfaces and automate the verification task for large regression simulation runs. Test coverage blocks track coverage metrics by extracting coverage statistics from the environment and the simulator, allowing engineers to accurately assess the level of testcase coverage and determine when test goals are met. Qualis has bundled all three of these core blocks into an easy-to-use DVC, and created an interconnect technology that makes plug-and-play building of layered verification environments a reality. The result is a powerful platform that supports all design implementation levels, including SoC/ASIC, FPGA, and board/system level.

Support for Industry-leading Testbench Tools

The Qualis DVC platform leverages the power of the two industry-leading testbench tools, Synopsys VERA and Verisity Specman Elite. As a charter member of both Synopsys' OpenVera(TM) Catalyst Program and Verisity's Verification Alliance(TM) partner programs, Qualis recognizes these two important testbench tools as the true "Verification Operating Systems" of the future. Through collaboration with Verisity and Synopsys, the new DVC platform will continue to support the latest enhancements to these languages and simulators, ensuring that engineers can count on full DVC compatibility, interoperability, and performance.

"Qualis' new Domain Verification Components complement our industry-leading verification tools, including VERA, VCS(TM) and Scirocco(TM)," said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys. "With Synopsys tools and Qualis DVCs, verification engineers can realize verification productivity gains to reduce total verification cycles."

Full Solutions in Functional Verification

Qualis also offers a premium level of customer support through its rich offering of consulting and training services. With the popular QuickRamp(TM) service package, new users of the DVC platform can go from zero knowledge of VERA and Specman to writing powerful testbenches for their designs in just a few weeks. Customers can tap into the deep verification knowledge of Qualis through its offering of advanced verification methodology courses and consulting services. More information can be found on the Qualis Web site.

Pricing and Availability

The growing family of Qualis Domain Verification Components is available today for Synopsys VERA and Verisity Specman Elite testbench tools and support interfacing to Verilog and VHDL designs. Components are available today for SONET, Utopia levels 1 and 2, ATM, SPI 4 phase 2, and Ethernet; a full listing of current and pending DVCs can be found on the Qualis Web site. Annual licenses start at US $7,500, with volume discounts available for customers who run large regression simulations. Each DVC comes with full documentation and example configurations for typical domain-specific environments. Qualis also offers full methodology training and support services for its DVCs, including its QuickRamp(TM) family of DVC deployment solutions. For more information, visit http://www.qualis.com/dvc.html.

About Qualis Design

Qualis Design is the leading independent verification methodology company offering a rich selection of productivity-enhancing Domain Verification Components(TM), methodology consulting, and best-in-class training services. By leveraging its deep experience in verifying networking, processor/SoC and wireless products, Qualis creates verification product solutions that solve the most challenging functional verification problems in the world. Users of Qualis revolutionary technology and verification methodology know-how build sustainable competitive advantages that keep them on the edge. Qualis is headquartered in Lake Oswego, Ore., and has development centers in Ottawa, Ontario; and Grenoble, France. To learn more, visit http://www.qualis.com/.

Note to Editors: Qualis and the Qualis logo are registered trademarks of Qualis Design Corp. DVC, Domain Verification Component and QuickRamp are trademarks of Qualis Design Corporation. Synopsys and VERA are registered trademarks of Synopsys, Inc. OpenVera, VCS and Scirocco are trademarks of Synopsys, Inc. Specman Elite is a trademark of Verisity Design, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.