QUICKLOGIC'S WEBESP DELIVERS GIGABIT ETHERNET TO POS-PHY LEVEL 3 SOLUTIONS.QuickLogic Corp. (Nasdaq:QUIK) has announced the company's patent-pending, web-based WebESP design environment can now deliver a high-speed Gigabit Ethernet to POS-PHY Level 3 (PL3) controller with packet rate transfers of up to 1.6 Gbps on the PL3 interface. QuickLogic's newest offering delivers a unique solution for system architects requiring single channel Gigabit Ethernet in applications such as access devices, routers, switches, test equipment, Packet over SONET/SDH Packet over SONET/SDH, abbreviated POS, is a communications protocol for transmitting packets in the form of the Point to Point Protocol over SDH or SONET, which are both standard protocols for communicating digital information using lasers or light emitting diodes (LEDs) (POS (1) See point of sale and packet over SONET. (2) "Parent over shoulder." See digispeak. POS - point of sale ) and Ethernet-over-Sonet. "As Gigabit Ethernet technology becomes widely available across the whole networking infrastructure, communications equipment manufacturers are looking for proven solutions that are optimized for their needs," said John Kim, QuickLogic's product marketing manager for embedded intellectual property. "Our single channel Gigabit Ethernet architecture delivers the required functionality with speed-to-market advantages." Built with standard interfaces, the new controller reduces design times by seamlessly connecting to industry standard Gigabit Ethernet PHY devices, network processor units or custom high layer processing devices. The product provides up to 1.6 Gbps packet rate transfers with a 104 MHz, 16-bit POS-PHY interface that exceeds the requirements for Gigabit Ethernet. It also implements full IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 802.3 compliant Media Access Controller (MAC) with preamble/SFD generation, as well as frame padding and CRC (Cyclical Redundancy Checking) An error checking technique used to ensure the accuracy of transmitting digital data. The transmitted messages are divided into predetermined lengths which, used as dividends, are divided by a fixed divisor. generation. The Gigabit Ethernet PHY device interface is enabled by a Gigabit Medium Independent Interface operating at 125 MHz. The controller has 2.5V and 3.3V compatible I/Os and is delivered in a 280-pin FPBGA FPBGA Fine Pitch Ball Grid Array package. Currently, WebESP's capabilities are focused on supporting a variety of communications-oriented applications, including multiplexers and bridges using Utopia I, Utopia II and Utopia III functions and POS-PHY L3. CSIX, PCI (1) (Payment Card Industry) See PCI DSS. (2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). , and LVDS (Low Voltage Differential Signaling) A transmission method for sending digital information. LVDS sends data over data high and data low lines rather than data and ground. SERDES See serializer/deserializer. functions will be added next. These building blocks were developed in close collaboration with MorethanIP (www.morethanIP.com), a development partner in QuickLogic's ongoing programs created to deliver more complete application-oriented solutions. Through the WebESP system, architects select the specific communications market/applications target and then design and configure the specific options for each function according to their own requirements. Once the design is completed, the engineer can review their design and release it for implementation. QuickLogic then creates the customer-specified devices and ships them directly to designers for immediate system development. Production volume requirements are available with QuickLogic's standard three-week lead-time. The QuickLogic's new Gigabit Ethernet to POS-PHY Level 3 controller is available now through the WebESP web page, www.quicklogic.com/webesp. |
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