QED introduces RM52xx microprocessor family; RM5230 and RM5260 delivers workstation-class performance to high-end embedded microprocessor market.SANTA CLARA, Calif.--(BUSINESS WIRE)--March 24, 1997--Quantum Effect Design, Inc. (QED QED abbr. Latin quod erat demonstrandum (which was to be demonstrated) QED which was to be shown or proved [Latin quod erat demonstrandum] Noun 1. ) today announced two new members of its RISCMark brand MIPS architecture microprocessor family - the RM5230 and RM5260. The RM5230 and RM5260 are derivatives of the R5000, which is currently shipping in high-performance systems including Silicon Graphics, Inc.'s O2 workstation and Cisco's 7500 high-performance routers. The RM52xx family provides workstation-class superscalar A CPU architecture that allows more than one instruction to be executed in one clock cycle. See pipeline processing. (architecture) superscalar - A superscalar architecture is a uniprocessor that can execute two or more scalar operations in parallel. microprocessor performance at an affordable price and is targeted at high-end embedded applications such as internetworking, printers, games, Internet TV/set-top boxes/cable modems and other high-speed communications devices markets. The RM52xx family features a superscalar instruction issue architecture that increases processor efficiency and performance. This architecture enables one integer and one floating point instruction to be processed within one microprocessor clock cycle, thereby achieving higher system performance without increasing clock speed. Superscalar processing is important for numeric algorithms found in DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive , imaging and 3-D applications as it enables computation and operand The part of a machine instruction that references data or a peripheral device. In the instruction, ADD A to B, A and B are the operands (nouns), and ADD is the operation code (verb). In the instruction READ TRACK 9, SECTOR 32, track and sector are the operands. access to occur in parallel. QED also announced it has established a North American North American named after North America. North American blastomycosis see North American blastomycosis. North American cattle tick see boophilusannulatus. sales network to sell its RISCMark labeled products (see press release "QED Names Sales Representatives," March 24, 1997). "We have found many customers who want the workstation-class floating-point and integer performance of a superscalar 64-bit CPU CPU in full central processing unit Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. , but need different memory architectures to meet system cost requirements," said Tom Riordan, QED president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. . "The RM5230 and RM5260 are excellent choices for customers who want the flexibility of developing or maintaining common software across multiple hardware platforms to meet different price/performance points." "The RM5230 microprocessor was designed and first samples were delivered to customers within 6 months," stated Riordan. "QED has responded to customers' demands for quick time-to-volume by rapidly designing and delivering high-performance embedded microprocessors that meet multiple price/performance points. The RM5230 and RM5260 were designed using QED's "Quick-Turn Microprocessor" technology, based on the `simple is better' design approach, and a design methodology that allows microprocessors to be easily ported to multiple foundries." RM5230 Product Description The RM5230 is a high-performance superscalar 64-bit microprocessor with a 32-bit memory interface and an estimated 2.7 SPECint95 rating, 2.5 SPECfp95 rating and 175 Dhrystone 2.1 MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. performance at 133 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. . It has 2.5 W typical power consumption at 3.3V and 133 MHz. It implements a DSP-enhanced MIPS IV instruction set architecture that includes the "Multiply/Add" (MULADD) and "Three-Operand Multiply" instructions. Key features of the RM5230 include: superscalar instruction issue, 5V tolerant I/Os, 16KB instruction cache and 16KB data cache (both 2-way set associative), full-featured MMU (Memory Management Unit) The part of the computer that governs memory access. Either part of the CPU chip or housed on separate chips, the MMU controls memory partitions and virtual memory. See memory and virtual memory. MMU - Memory Management Unit compatible with the R4600, R4700 and R5000 microprocessors, low system cost 32-bit memory interface with 67 MHz maximum operation and 1149.1 compliant JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology. JTAG - Joint Test Action Group boundary scan functionality for manufacturing testing. The RM5230 is manufactured using leading-edge 0.35 micron technology at TSMC TSMC Taiwan Semiconductor Manufacturing Company, Ltd TSMC Taiwan Semiconductor Manufacturing Corporation TSMC Traffic Systems Management Center TSMC Toll Station Management Controller TSMC Transportation Supply Maintenance Command TSMC Technical Services Manager Code (Taiwan) with assembly and testing at Amkor/Anam (Korea). RM5260 Product Description The RM5260 is a high-performance superscalar 64-bit microprocessor with a 64-bit memory interface and an estimated 3.0 SPECint95 rating, 2.8 SPECfp95 rating and 200 Dhrystone 2.1 MIPS performance at 150 MHz. It has a 2.8 W typical power consumption at 3.3V and 150 MHz. It implements a DSP-enhanced MIPS IV instruction set architecture that includes the "Multiply/Add" (MULADD) and "Three-Operand Multiply" instructions. Key features of the RM5260 include: superscalar instruction issue, 5V tolerant I/Os, 16KB instruction cache and 16KB data cache (both 2-way set associative), full-featured MMU compatible with the R4600, R4700 and R5000 microprocessors, high-performance 64-bit memory interface with 75 MHz maximum operation and 1149.1 compliant JTAG boundary scan functionality for manufacturing testing. The RM5260 is manufactured using leading-edge 0.35 micron technology at TSMC (Taiwan) with assembly and testing at Amkor/Anam (Korea). RM52xx Product Family: Targeted At High-End Embedded Market "Customers like the fact that in 1996, over 19.2 million MIPS RISC processors were shipped making the MIPS architecture the fastest-growing RISC RISC in full Reduced Instruction Set Computing Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s. architecture in the world," said Rick Kepple, QED vice president of marketing and sales. "We have seen other microprocessor architectures run out of gas when it comes to meeting the performance requirements of the high-end embedded market. Customers want more than promises of roadmaps, they want to know their strategic investment in a microprocessor architecture will be protected in the long term. QED's RM52xx family of high-performance MIPS architecture microprocessors are providing such a roadmap today." "Looking beyond our current offering of high-performance microprocessors, QED is evaluating whether to add architectural extensions like MDMX or MIPS16 and/or possibly integrate system functions like PCI (1) (Payment Card Industry) See PCI DSS. (2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). and SDRAM (Synchronous DRAM) A type of dynamic RAM (DRAM) memory chip that has been widely used since the late 1990s. SDRAM chips eliminated wait states by dividing the chip into two cell blocks and interleaving data between them. to our microprocessors," Kepple stated. "These new products will help meet the market demand for affordable high-performance microprocessors." Tools Support for RM5230 and RM5260 QED is supporting embedded designers' requirements with a wide range of software and hardware tools for the RM5230 and RM5260. Algorithmics, Ltd. (London, UK), in cooperation with QED, currently supports the RM5230 with its "SDE-MIPS" Compiler, Assembler, Linker and Debugger software tools and hardware evaluation board. Algorithmics is also slated to provide the RM5260 versions of the SDE-MIPS software development tools and hardware evaluation board in 2Q97. Galileo Technology, Inc. (San Jose, CA) is planning to provide a RM5260 hardware evaluation board with RTOS (1) (RealTime Operating System) An operating system designed for use in a real time computer system. See real time system, embedded system, process control and OS-9. support in 2Q97. RM5230 and RM5260 microprocessor logic analyzer support is planned by Corelis (Cerritos, CA) for Hewlett-Packard pre-processor pods and disassembler Software that converts machine language back into assembly language. Since there is no way to easily determine the human thinking behind the logic of the instructions, the resulting assembly language routines and variables are named and numbered generically (A001, A002, etc.). software and by Crescent Heart Software (Portland, OR) for Tektronix adapter pods and disassembler software. Packaging, Availability and Pricing Samples of the RM5230 are available now, with production volumes scheduled for 3Q97. The RM5230 is available at 100 and 133 MHz in a 128-pin Power-Quad 4 package with prices starting below $35 in 10,000-piece quantities. Samples of the RM5260 are available now, with production volumes scheduled for 3Q97. The RM5260 is available at 133 and 150 MHz in a 208-pin Power-Quad 4 package with prices starting below $75 in 10,000-piece quantities. About Quantum Effect Design, Inc. Quantum Effect Design, Inc., founded in 1991, designs, develops and markets high-performance, cost-effective, market-driven embedded microprocessor solutions. The company designed and developed many of the 64-bit MIPS microprocessors including the popular R4600, R4700, R4650 , R4640, R5000 and under its own "RISCMark" label, the RM5230, RM5260 and RM7000. Quantum Effect Design's RM52xx and RM7000 product families include high-end, 32- and 64-bit embedded microprocessors targeted at emerging and fast-growing markets such as internetworking, printers, games, Internet TV/set-top boxes/cable modems and high-speed communications devices. The company has an unsurpassed record of designing and delivering innovative high-performance microprocessors in breakthrough time-to-volume. Company headquarters are located in Santa Clara, California Santa Clara, California (IPA: /ˌsæntəˈklærə/) , founded in 1777 and incorporated in 1852, is a city in Santa Clara County, in the U.S. state of California. . Telephone: 408/565-0300. QED World Wide Web site: http://www.qedinc.com . -0- Note to Editors: MIPS is a registered trademark and R5000 a trademark of MIPS Technologies, Inc., R4600, R4700, R4650, and R4640 are trademarks of Integrated Device Technology IDT (NASDAQ: IDTI) was founded in 1980 as a semiconductor vendor. Employing approximately 2500 people worldwide, headquartered in San Jose, California and operating a fab in Hillsboro, Oregon, the company both designs and fabricates semiconductor components. , Inc., Power-Quad 4 is a trademark of Amkor/Anam, and RISCMark, RM5230, RM5260, RM52xx and RM7000 are trademarks of Quantum Effect Design, Inc. and O2 is a trademark of Silicon Graphics, Inc. CONTACT: Quantum Effect Design Rick Kepple, 408/565-0315 rkepple@qedinc.com or Simon/McGarry Public Relations public relations, activities and policies used to create public interest in a person, idea, product, institution, or business establishment. By its nature, public relations is devoted to serving particular interests by presenting them to the public in the most Sandra McBride/Melanie Laurence, 408/746-0911 smcbride@shandwick.com |
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