Pentium, The Fourth: Finally, More Than Just Megahertz.

Taking a look inside Intel's architecture advances

Another new year, another new CPU from Intel. With the possible exception of Intel executives, those in the industry barely register excitement when it comes to yet another new Intel chip. But while the new chips come with associated new speeds, the design advances in Intel's new chips are more interesting and, generally, more relevant to the work that most of us actually perform. Unfortunately, most consumers are more interested in core processor speed, which generally has little or no bearing on the work they actually do.

But unlike the chips introduced by the processor powerhouse last year, this year's CPU, the Pentium 4, includes a brand new micro-architecture, called NetBurst, an important new chipset, and a brand new system bus design. In addition, it's helpful to examine Intel's architecture advances, because most of them are now reproduced (albeit with different monikers) by AMD Corp.

Intel says that the P4 processor is the company's first completely new desktop processor since the Pentium Pro, with its P6 micro-architecture, was introduced in 1995. The P4 includes what Intel calls Hyper Pipelined Technology. This is advanced internal processing architecture which builds upon the superscalar design of the PIII. Hyper Pipelined Technology enables the Pentium 4 processor to execute software instructions in a 20-stage pipeline, as compared to the 10-stage pipeline of the Pentium III processor. The new technology also supports a new range of clock speeds, including 1.4GHz and 1.5GHz chips, which should be available in systems by the time you read this. Speeds of at least 2GHz are expected by the third quarter of this year.

The Pentium 4 offers a marked increase in transistors from the Pentium III: 42 million versus the older chip's 28 million. A new technology called Execution Trace Cache offers a wrinkle in standard Level 1 cache design. Execution Trace Cache caches previously decoded x86 instructions, which Intel says removes the performance penalty associated with using the instruction decoder in the chip's main execution loops. Another new technology, Advanced Transfer Cache, works with Level 2 cache to increase performance in transferring instructions to the processor core. Advanced Transfer Cache consists of a 256-bit (32 byte) interface that transfers data on each core clock cycle. This means that the P4 offers a transfer rate of 44.8GB per second: 32 bytes x 1 (data transfer per clock cycle) x 1.4GHz (core processor speed) = 44.8GB per second. This contrasts with 16GB per second for the 1GHz Pentium III.

In marked contrast to the debacle of the 1GHz Pentium III introduction, where that chip was introduced yet unavailable to OEMs for six months, Intel officials indicated that the chips will ship to OEMs in volume immediately following the rollout. But like the introduction of the 1.13GHz PIII, initial reports indicate that early shipments of the P4 contained chips that were missing some critical code. Fortunately, at least at press time, these chips had been recalled before they made it into the hands of consumers.

SDRAM Need Not Apply

As expected, the Pentium 4 chip supports a 400 MHz system bus, surpassing--for the moment, anyway--the AMD Athlon bus speed. However, in order to take advantage of such speeds, users will have to purchase systems with Intel's new 850 chipset, also announced with the P4. The 850 chipset supports only Rambus RDRAM, not lower-cost (and slower) SDRAM and DDR SDRAM. Intel expects other manufacturers to offer chipsets that support both the P4 and SDRAM.

Intel's 850 chip set finally takes full advantage of Intel's memory controller hub (MCH) architecture, which eliminates the legacy northbridge/southbridge architecture used in virtually all earlier Pentium designs. Previous Pentium processors and Pentium-based systems included a northbridge bus, which is the faster bus that connects the CPU, main memory, and AGP graphics adapter. The slower southbridge uses the 133MHz PCI bus to connect slower system components, including ISA, USB, and serial devices. The P4 finally eliminates this configuration in favor of the memory controller hub which connects to the CPU, system memory, and the AGP bus at 3.2GBps (1.6GBps per dual channel for RDRAM). The MCH now uses a 266MB bus to connect to a new I/O Controller Hub (ICH2) which connects to other buses and peripherals. The figure shows the various bus connections and throughput speeds.

The Pentium 4 also includes what Intel refers to as a "Rapid Execution Engine" which allows frequently used Arithmetic Logic Unit instructions to be executed at double the core clock. In addition, 144 new instructions have been added to further speed the processing of video, audio, and 3D applications. Additional advances include:

* Two USB controllers, which doubles the bandwidth available for USB peripherals to 24Mbps over four ports.

* AC97 audio support for six channels of audio.

* A LAN Connect Interface (LCI), which supports home phoneline and 10/100Mbps Ethernet, and 10/100Mbps Ethernet with LAN manageability. All three network options will use Intel's SingleDriver Technology, which supports multiple products.

* Dual Ultra ATA/100 controllers.

* A Communication and Networking Riser (CNR), which can be upgraded with an audio, modem, or network card.

The two new Pentium 4 chips will cost $644 (1.4GHz) and $819 (1.5GHz) in volume; this makes them significantly cheaper than the 1GHz PIII was in March of 2000, when it was announced at $990 in volume. Systems based on the chips are expected from all the major OEMs, with initial pricing ranging from about $2,000 to as much as $3,500, depending on configuration and memory. At press time, Compaq, Dell, Gateway, IBM, and NEC had all announced forthcoming P4-based systems.

Performance Gains? Perhaps...

The key question, of course, is whether the average user (as opposed to the power user or gamer) will encounter any discernable performance improvements during his or her day-to-day computing tasks. That depends on the task. Users performing multimedia creation tasks (video coding, MP3 ripping) will likely see some gain from the P4's new Streaming SIMD Extensions 2 (SSE2) instructions, provided the application being used takes advantage of them. Similarly, floating-point, computationally intensive tasks will gain some performance from both faster clock speeds and from the chip's internal branch prediction mechanisms (as well as from RDRAM, if used).

But even Intel admits that, for the vast majority of users running productivity apps (Word, Excel, Navigator and IE, Outlook), improvements at the micro-architecture level (such as the Pentium 4's 20-stage hyper pipeline) will offer few noticeable gains in performance. Noticeable is the key word here, because while the application itself may gain some speed internally, these types of applications need only keep pace with human levels of read and write times, which are satisfied by existing Pentium III chips. In addition, productivity applications include code which is not especially ordered or predictable, which will necessarily limit gains in the chip's branch prediction mechanisms, mechanisms that rely on predictable code to increase performance.

As is typical for new chips from Intel, users will likely see more gains from the faster graphics and disk subsystems used by OEMs in the high-end machines that feature brand new chips, no matter what their speed. Martin Reynolds, chief microprocessor analyst at Gartner Group, says that the real performance gains will come next year, when the P4 ramps up to 3GHz. Reynolds believes that AMD's Athlon will continue to sell well against the P4 in the near term, but says that the current Athlon will run out of steam in 2001. "AMD will need to revise the architecture to catch up," Reynolds says.

Some interesting news--news which was not included in the P4 announcement--is that Intel has finally broken the .18 micron roadblock, and has now completed development of its .13 micron-based processor logic. Unfortunately, this new process technology does not appear in the current versions of the P4, which are based on Intel's existing .18 micron fabrication process. (At press time, Intel was scheduled to present details of its new process technology at the International Electron Devices Meeting. in December, and will begin volume manufacturing next year.)

But, as expected, Intel will not be alone in producing .13 micron chips. IBM, Infineon, and UMC have announced that they too have begun building chips with .13-micron foundry process technology. The companies claim that their chips will have the highest number of copper wiring layers in the industry. First customer shipments of the new high performance chips are expected early in 2001.