Paying to spend less: why embedding parts can reduce overall systems costs even while bare-board prices rise.COST, PERFORMANCE, FUNCTIONALITY and size: These are the drivers for embedded Inserted into. See embedded system. passive technology that meet with institutional (IPC (1) (InterProcess Communication) The exchange of data between one program and another either within the same computer or over a network. It implies a protocol that guarantees a response to a request. , IMAPS IMAPS IMAP (Internet Message Access Protocol) Secure IMAPS International Microelectronics And Packaging Society IMAPS Interstellar Medium Absorption Profile Spectrograph IMAPS Integrated Military Airlift Planning System (MAC) , NEMI NEMI National Electronics Manufacturing Initiative NEMI National Environmental Methods Index , many large OEMs) consensus. Cost is the driver that attracts the most attention. I have derived this from numerous discussions with the buying community, including purchasing agents Noun 1. purchasing agent - an agent who purchases goods or services for another agent - a representative who acts on behalf of other persons or organizations , board designers and project engineers. "How much less does the PCB PCB: see polychlorinated biphenyl. PCB in full polychlorinated biphenyl Any of a class of highly stable organic compounds prepared by the reaction of chlorine with biphenyl, a two-ring compound. cost when you embed em·bed also im·bed v. em·bed·ded, em·bed·ding, em·beds v.tr. 1. To fix firmly in a surrounding mass: embed a post in concrete; fossils embedded in shale. the passives?" they always ask. Let's be clear on cost as it relates to bare PCBs. The IMS (1) See IP Multimedia Subsystem. (2) (Information Management System) An early IBM hierarchical DBMS for IBM mainframes. IMS was widely implemented throughout the 1970s under MVS and continues to be used under z/OS. community--PCB manufacturers--will not sell boards at lower prices after adding process steps (and more-expensive materials), testing and verification, and experiencing lower yields and assuming greater liability. Sell the PCBs cheaper? It will never happen--not in North America North America, third largest continent (1990 est. pop. 365,000,000), c.9,400,000 sq mi (24,346,000 sq km), the northern of the two continents of the Western Hemisphere. , not in Europe and not even in Asia. >From where does this notion come? The answer seems obvious. In the institutional EP driver language, lower cost is intended to imply lower system cost. To many, "system" is ignored or not understood, and mistaken as lower PCB costs. Can bare board costs be lower? Sometimes, conditions being just right. This makes the reduced system costs even more attractive. Are bare-board costs always lower? No. Can bare-board costs be higher and systems costs lower? Absolutely! That is typical, and that is what makes the cost driver work. Embedding 1. (mathematics) embedding - One instance of some mathematical object contained with in another instance, e.g. a group which is a subgroup. 2. (theory) embedding - (domain theory) A complete partial order F in [X -> Y] is an embedding if passive components can result in a more efficient PCB manufacturing process by increasing the number of boards on the panel. There are rare (emphasis on rare) instances where this alone can result in a lower unit cost of the bare boards. In the bare circuit board manufacturing trade, we commonly say, "We don't build boards, we build panels." There are many standard panel sizes used in manufacturing, the most common being 18 x 24". I'll use that in this example. Since 0.75 to 1" of border is typical, the resulting usable USable is a special idea contest to transfer US American ideas into practice in Germany. USable is initiated by the German Körber-Stiftung (foundation Körber). It is doted with 150,000 Euro and awarded every two years. board area is approximately 16 x 22". This border is for registration tooling holes (lamination lamination a laminar structure or arrangement. , drilling, imaging), plating thieving, support and stability of innerlayers, product identification and traceability. Adding test coupons for IPC-6012 Class 2 or 3 microsections, impedance impedance, in electricity, measure in ohms of the degree to which an electric circuit resists the flow of electric current when a voltage is impressed across its terminals. control, registration and IST will reduce the usable area to 16 x 20" or smaller. Simply stated, the board cost equals the cost of materials, plus labor, overhead and profit. What are materials? There are direct materials--those that become the board; and there are indirect materials--those that are consumed in the process of making the board. Direct materials include laminate laminate, n a thin slice of porcelain or plastic fabricated in a dental lab, which is cemented to the front of the teeth to cover gaps, whiten stained teeth, or reshape chipped or broken teeth. , prepreg, embedded passive materials, soldermask, legend ink, copper, and finishes such as solder solder (sŏd`ər), metal alloy used in the molten state as a metallic binder. The type of solder to be used is determined by the metals to be united. Soft solders are commonly composed of lead and tin and have low melting points. Hard solders (i. , nickel nickel, metallic chemical element; symbol Ni; at. no. 28; at. wt. 58.69; m.p. about 1,453°C;; b.p. about 2,732°C;; sp. gr. 8.902 at 25°C;; valence 0, +1, +2, +3, or +4. , gold, tin, silver, etc. These have a predictable and known cost and are allocated to a specific product. Indirect materials, on the other hand, are consumed in the manufacturing process, are used for virtually all products, and their costs are typically allocated across all jobs on a percentage basis. Let's look closer at panelization efficiency, i.e., the number of parts on the panel (number up). Since we manufacture panels, the bulk of the costs are associated with the panel and are only moderately affected by the number of boards on the panel. Hence, the greater the number of boards on the panel, the lower the unit cost. TABLE 1 illustrates the board size for a variety of numbers up. In this example, the panel is 18 x 24", has typical borders, IPC-6012 Class 3 coupon strips (two each), four-track impedance coupon (one each), and 0.1" board spacing. The "basis" board is prior to any reduction in surface area. The "minus" 10%, 20% and 30% represent reductions in surface area and the relative change in panel efficiency (number up). TABLE 2 illustrates the surface area consumed by several standard SMT (1) (Surface Mount Technology) See surface mount. (2) (Station ManagemenT) An FDDI network management protocol that provides direct management. Only one node requires the software. SMT - Station Management package sizes. TABLE 3 illustrates the total surface area used as a function of the quantity of SMT packages embedded. In short, SMT packages take up space. With this information, assume that our initial design without embedding is an eight-layer 14.7 [in.sup.2] board. Analysis indicates that we are able to embed a total of 330 0603 capacitors and 330 0402 resistors. The total reduction in SMT surface is 4.1 [in.sup.2]. Assuming our board profile is reduced proportionately pro·por·tion·ate adj. Being in due proportion; proportional. tr.v. pro·por·tion·at·ed, pro·por·tion·at·ing, pro·por·tion·ates To make proportionate. in the x and y dimensions, our resulting board will be 10.6 [in.sup.2]. The resultant This article is about the resultant of polynomials. For the result of adding two or more vectors, see Parallelogram rule. For the technique in organ building, see Resultant (organ). In mathematics, the resultant of two monic polynomials panel efficiency increases by 20% to 24 up. Although the PCB unit price is proportional to the number up, it is not absolutely linear. We will assume, in this case, that the reduction in basis board price relates to 85% of the gain in panel efficiency, or equivalent to 23.4 up rather than 24 up. The costs of embedding passives are tabulated in TABLE 4. First, let's look at the capacitors. Assume our analysis shows that the capacitors can be embedded using a high Dk planar A technique developed by Fairchild Instruments that creates transistor sublayers by forcing chemicals under pressure into exposed areas. Planar superseded the mesa process and was a major step toward creating the chip. material. To achieve the capacitance capacitance, in electricity, capability of a body, system, circuit, or device for storing electric charge. Capacitance is expressed as the ratio of stored charge in coulombs to the impressed potential difference in volts. density required, it takes two layer pairs of this material in a power and ground configuration, with the power close to the surface, probably layer 2 or possibly even layer 1. The original design delivered power to the BGAs from a single power plane and returned through a single ground plane. To provide the required capacitance, an additional layer pair is necessary and will be designed as a parallel capacitor capacitor or condenser, device for the storage of electric charge. Simple capacitors consist of two plates made of an electrically conducting material (e.g., a metal) and separated by a nonconducting material or dielectric (e.g. to the original P/G P/G Grace Under Pressure (Rush album) planes. The cost of processing this material is modestly higher than a conventional layer due to the thinness of the material. This is estimated at a 20% processing cost increase. If the basis cost of processing a layer is $10, then the added processing cost for the layer is $2. The added processing cost for the substitute layer is $2 plus the processing cost of $12 for the new layer, a total of $14. For the raw material costs, to keep the math simple, assume that the basic FR-4 raw material is $10 for a layer pair. The cost of the high Dk raw material is 4X the basic FR-4 dielectric dielectric (dī'ĭlĕk`trĭk), material that does not conduct electricity readily, i.e., an insulator (see insulation). A good dielectric should also have other properties: It must resist breakdown under high voltages; it should not used in the design. Then the added material cost for changing one layer pair to a high Dk laminate will be $40 for the additional layer pair material minus the original $10 allowance, a total of $30. The added material cost for the new layer pair will be $40, giving a total of $70 additional capacitor materials. Add the processing cost of $14 and we have a total of $84 materials and processing for the embedded capacitors. We calculate resistor resistor, two-terminal electric circuit component that offers opposition to an electric current. Resistors are normally designed and operated so that, with varying levels of current, variations of their resistance values are negligible (see resistance). costs using similar logic. Assume that performance dictates the use of ceramic This article is about ceramic materials. For the fine art, see Ceramic art. The word ceramic is derived from the Greek word κεραμικός (keramikos). thick-film technology. All resistors can be designed and manufactured on a single layer using two paste values. Further, no additional routing signal layers are required. The added cost for materials and fabricating the CTF CTF Capture The Flag CTF Child Trust Fund (UK) CTF Canadian Tax Foundation CTF Canadian Taxpayers Federation (lobby group) CTF Canadian Television Fund CTF Canadian Teachers' Federation foil and core is $200. The added cost for trimming and testing the resistors is an additional $100. This includes layer test and trimming, plus final board resistance testing. The total added cost per panel for embedding resistors and capacitors is $384. Assuming that the basis board is eight layers and the panel added value Added value in financial analysis of shares is to be distinguished from value added. Used as a measure of shareholder value, calculated using the formula:
How could an IMS firm be expected to manufacture this board at a price below the basis board price? The board price cannot be below $22.82, a 204% increase. We have to look at the off-setting component and assembly costs. Assume that the average resistor and capacitor combined part price and assembly is 2 cents each. Since we are embedding a total of 660 parts, the assembly costs are $13.20. Adding this to our basis board price, the assembled passive board is $20.70. Now we are making progress. The embedded bare board price ($22.82), less the part and assembly cost ($13.20), is $9.62. This is $11.08 less than the conventional assembled passive board price--a 54% reduction. So this is my message: Embedding 660 passive components may increase the bare-board unit price by more than 200% and at the same time reduce the assembled passive board cost by greater than 50%. That's cost reduction, folks. The IMS firms have to work harder, spend more on materials and processes, and take more risks to affect a significant systems--cost savings. Is there anything wrong with this picture? To me, it's fair compensation for honest work.
TABLE 1. Panel Efficiency
NO. UP X Y AREA ([in.sup.2])
BASIS 1 15.45 20.11 310.7
4 7.67 10.00 76.7
20 3.62 4.07 14.7
40 2.88 2.50 7.2
-10% 1 14.68 19.10 280.4
4 7.29 9.50 69.2
20 3.44 3.87 13.3
42 2.74 2.38 6.5
-30% 1 13.13 17.09 224.5
4 6.52 8.50 55.4
24 3.08 3.46 10.6
54 2.45 2.13 5.2
-50% 1 10.97 14.28 156.6
6 5.45 7.10 38.7
35 2.57 2.89 7.4
72 2.04 1.78 3.6
TABLE 2. Package Areas
PACKAGE PART SIZE (in) AREA ([in.sup.2]) *
0201 0.020 0.010 0.0032
0402 0.040 0.020 0.0051
0603 0.060 0.030 0.0074
0805 0.080 0.050 0.0118
* Including footprint, via pads and keep out area.
TABLE 3. Multiple Package Areas
AREA ([in.sup.2]) VS. QTY. OF PACKAGES
PACKAGE 100 250 500 1000
0201 0.319 0.798 1.596 3.192
0402 0.509 1.273 2.546 5.092
0603 0.739 1.848 3.696 7.392
0805 1.183 2.958 5.916 11.832
TABLE 4. Cost of Embedding
BASIS ADDER (%) ADDER TOTAL
COST OF EMBEDDING CAPACITOR LAYERS
Process thin material
Existing P/G layer pair $10 20%/layer $2
New P/G layer pair $12 100% $12
Material
New layer pair $40 100% $40
Replacement layer pair
($40 new material minus $10
existing material) $30
Total capacitor $84
COST OF EMBEDDING RESISTOR LAYERS
Process foils and cores $150
Trim and test cores and test boards $150
Total resistor $300
Total embedding cost per panel $384
TABLE 5. System Costs
X Y AREA ([in.sup.2])
BASIS SMT ASSEMBLED BOARD
Board 3.62 4.07 14.7
Parts (660 @ $.012 ea.) $7.92
Assembly (660 @ $.008 ea.) 5.28
Total assembled passives with PCB $20.70 0.0%
EMBEDDED BOARD
330 ea. 0402 1.68
330 ea. 0603 2.44
New board size 3.08 3.46 10.6
Price affect (85% gain)
Capacitor panel cost
Resistor panel cost
Total embedded board cost
OFF-SET COSTS
Parts (660 @ $.012 ea.) 7.92
Assembly (660 @ $.008 ea.) $5.28
Total off-set
EMBEDDED SYSTEM COST
ORIGINAL SYSTEM COST
NET SYSTEM COST REDUCTION
#UP PANEL PRICE UNIT PRICE % CHANGE
BASIS SMT ASSEMBLED BOARD
Board 20 $150 $7.50
Parts (660 @ $.012 ea.)
Assembly (660 @ $.008 ea.)
Total assembled passives
with PCB
EMBEDDED BOARD
330 ea. 0402
330 ea. 0603
New board size 24
Price affect (85% gain) 23.4%
Capacitor panel cost $84
Resistor panel cost $300
Total embedded board cost $532 $22.82 +204%
OFF-SET COSTS
Parts (660 @ $.012 ea.)
Assembly (660@$.008 ea.)
Total off-set $13.20
EMBEDDED SYSTEM COST $9.62
ORIGINAL SYSTEM COST $20.70
NET SYSTEM COST REDUCTION $11.08 -54%
RICHARD SNOGREN is a member of the technical staff at Coretec Inc. (coretee-inc.com). He can be reached at rsnogren@coretec-denver.com. |
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