Package routing considerations: left uncompensated for, IC packages can skew the routing process. How to keep your timing tight.

HIGH PERFORMANCE SYSTEM-LEVEL memory architectures such as Rambus and QDR means PCB designs with subnanosecond interconnect timing budgets. Device technologies that in the past have provided programmable I/O cell timing to compensate for interconnect length variations have difficulty supporting the very high speed timing requirements of these busses.

When designing PCBs containing circuits of this nature, IC package interconnect are considered together with PCB routing structures to meet bus-timing specifications. Routing PCBs with consideration for IC package interconnects requires that designers constrain signal routing with very tight unique net-level delay targets.

Low-cost, high lead-count VLSI devices such as processors and FPGAs commonly incur package interconnect skew because fine pitch I/O lands on the die must fan out to a much larger and coarser pitch array of device lands within the package on a small number of area-limited package routing layers. A review of IC package interconnect lengths within common bus circuit signals will reveal whether PCB routing will need to compensate for package routing skew.

If, for example, your die-to-die interconnect timing margin allows for only 400 psec of delay, all it takes is 10 mm (0.393") of package interconnect length variation between common bus signals to eat up 35% of your timing budget, based on a worst-case package skew on both ends and an interconnect propagation velocity of 7 psec/mm (180 psec/in.). Such a variation in timing considered with all other sources of timing skew--IC process and temperature variations, for instance--can have a disastrous effect on production yield if the PCB routing solution does not correct for them.

Device vendors must supply detailed package interconnect lengths as well as propagation velocity estimates due to the unique materials used in their package substrates to support accurate PCB signal integrity modeling and layout efforts.

Detailed PCB routing can begin as soon as targets for board-level interconnects are developed. This process will sum individual Manhattan distances between source and load device package pins for each signal with their corresponding IC package routed interconnect length based on a preliminary placement. To simplify constraint development, the IC packages' lengths will be corrected based on the package propagation velocity to match tire propagation velocity of the target PCB construction. This method provides a good first-order skew approximation for common groups of I/O cells recognizing that actual signal propagation velocity will vary due to circuit loading characteristics.

Source-to-load flight lengths are documented within a spreadsheet for all single-and multiple-load PCB routing topologies. Pay close attention to the differences between a device vendor's signal-naming convention as compared to signal names used in your board-level design so that compensation is applied correctly. I recommend re-ordering the device vendor package signal names in the rule development spreadsheet to align with a natural sorting of signal names in your design. Doing so simplifies the later import of PCB length report data generated for each potential routing solution.

Manhattan distances are common by de-rated to permit some inefficiency in the final routing solution. The extent of adjustment will hinge on routing density and local areas of high routing density in and around fine-pitch, high pin-count devices. In some cases Manhattan lengths must he taken from a placed version of the PCB design where SMD escape routing has already been completed and imported into the rules development spreadsheet to better approximate the final routing solution.

Pre-routing simulations are performed across worst-case model and PCB construction variations whose models include signal-level package interconnect to identify the slowest circuits within bus groups and to refine the Manhattan based PCB routing target flight length values for each source load pair on each signal. This step will help to further reduce interconnect skew, and maximize setup and hold timing margins for clocking and control circuits with consideration for circuit loading.

The IC package-compensated PCB routing targets are then extracted directly from the final rule development spreadsheets into routing constraints using an alternative spreadsheet format already set up to conform to the target PCB layout tools used for autorouting. When routing is complete, source-to-load PCB interconnect flight length reports are generated and imported into actual columns (Figure 1). The final rule development spreadsheet is a final confirmation that routing has met target specifications and can be an improved guide for further rule and routing strategy development.

TABLE 1. An IC package-compensated PCB routing rule sheet

DEVICE        DEVICE      DESIGN SIGNAL
SIGNAL        LENGTH

RDR1_CFM      9672        /DELUXE RMB1_ CFM
RDRI_CFMN     9674        /DELUXE_RMB1 CFM_N
RDR1_CMD      13436       /DELUXE_RMB1_CMD
RDR1_CTM      12643       /DELUXE_RMB1_CTM
RDRI_CTMN     12645       /DELUXE_RMB1_CTM N
RDR1_DQA[0]   11567       /DELUXE_RMB1_DQA(0)
RDRI_DOA[1]   9603        /DELUXE_RMB1_DQA(1)
RDR1_PCLKM    3466        /DELUXE_RMB1_PCLKM
RDRI_RQ[0)    10391       /DELUXE_RMB1_RQ(0)
RDR1_RQ[1]    9432        /DELUXE_RMB1_RQ(1)
RORl_RQ[2]    8143        /DELUXE_RMB1_RQ(2)
RDR1_SCK      3641        /DELUXE_RM81_SCK
RDRI_SIO      6608        /DELUXE_RMB1_SIN
ROM_SCLKN     10610       /DELUXE_RMB1_SYNCLK_N

DEVICE         SOURCE       LOAD
SIGNAL

RDR1 CFM      U200-C22    U204-A27
RDRI CFMN     U200-C21    U204-A28
RDR1_CMD      U200-A13    U204-A63
RDR1_CTM      U200-A22    U204-A69
RDRI_CTMN     U200-A21    U204-A68
RDR1_DQA[0]   U200-A23    U204-A26
RDRI_DOA[1]   U200-C23    U204-A67
RDR1_PCLKM    U200-D14    U204-A20
RDRI_RQ[0)    U200-A17    U204-A32
RDR1_RQ[1]    U200-BI8    U204-A73
RORl_RQ[2]    U200-D18    U204-A31
RDR1_SCK      U200-D13    U204-A22
RDRI_SIO      U200-F14    U204-A94
ROM_SCLKN     U200-B13    U204-A60

DEVICE        LENGTH      TARGET
SIGNAL        (MM)

RDR1 CFM       95.34903    95.38
RDRI CFMN      95.38273    95.38
RDR1_CMD       97.89477    97.89
RDR1_CTM       92.70671    92.84
RDRI_CTMN      92.75544    92.84
RDR1_DQA[0]    93.65471    93.76
RDRI_DOA[1]    95.36595    95.44
RDR1_PCLKM    101.3513    106.42
RDRI_RQ[0)     94.63789    94.77
RDR1_RQ[1]     95.51738    95.59
RORl_RQ[2]     96.63784    96.69
RDR1_SCK      101.26703   106.27
RDRI_SIO      102.92421   103.74
ROM_SCLKN     99.51408    100.31

DEVICE        TOTAL       DIFFSKEW               STATUS
SIGNAL        (MM)          (MM)

RDR1 CFM      103.62        0.03                   OK
RDRI CFMN     103.66        0.03                   OK
RDR1_CMD      109.39                               OK
RDR1_CTM      103.52        0.05                   OK
RDRI_CTMN     103.57        0.05                   OK
RDR1_DQA[0]   103.55                               OK
RDRI_DOA[1]   103.58                               OK
RDR1_PCLKM    104.32                          OUT OF SPEC
RDRI_RQ[0)    103.53                               OK
RDR1_RQ[1]    103.59                               OK
RORl_RQ[2]    103.6                                OK
RDR1_SCK      104.38                          OUT OF SPEC
RDRI_SIO      108.58                          OUT OF SPEC
ROM_SCLKN     108.59                          OUT OF SPEC

Minimum LVTTL Length:   104.32
Maximum LVTTL Length:   109.39
Minimum RSL Length:     103.53
Maximum RSL Length:     103.66

BERNARD VOSS is the principle interconnect specialist at the consulting group Stilwell Baker Inc. (stilwellbaker.com). He has been in the interconnect design business for over 20 years, engineering interconnect solutions for hardware development teams worldwide.