PMC-Sierra Samples RM9000x2 64-Bit MIPS-based Multiprocessor Running at 1.0 Gigahertz with Integrated Memory and I/O Interfaces.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--Oct. 14, 2002

RM9000x2's Dual 1.0 Gigahertz Processors Deliver Unprecedented

Performance for High-End Networking, Enterprise, and Wireless

Applications

PMC-Sierra (Nasdaq:PMCS) today announced that it is sampling its highly integrated RM9000x2(TM) 64-bit MIPS-based dual processor. Manufactured in an industry-leading .13-micron, low-k copper process, the RM9000x2 device is running the Linux operating system at 1.0 Gigahertz (GHz). The RM9000x2 solution draws less than 10 watts of total device power with each processor running at 1 GHz and all of the memory and I/O interfaces running at maximum frequency. The RM9000x2 integrates multiple high-speed bus interfaces, which include HyperTransport(TM), DDR SDRAM, SysAD and a boot bus, to enable low latency access to main memory and high bandwidth to external I/O devices (see figure 1). The RM9000x2 targets high-touch, performance-driven applications such as edge routers, DSLAMs and wireless base stations.

RM9000x2 Optimized for Performance

"Our unique architecture provides networking and communications equipment designers greater processing power by integrating multiple GHz CPU cores with next-generation, high-speed bus interfaces," said Tom Riordan, vice president and general manager of PMC-Sierra's MIPS Processor Division. "The RM9000x2 CPU subsystem is optimized for highest performance, and gives designers the flexibility to develop both control and data plane applications."

"PMC-Sierra's track record in delivering high-performance MIPS-based processors has once again been demonstrated by delivering the RM9000x2 at the intended target processor speed of 1 GHz," said Markus Levy, senior analyst at MicroDesign Resources and president of EEMBC. "The RM9000x2 dual core architecture was well designed for the high performance, flexibility and low power requirements of high-end networking applications."

RM9000x2 CPU Subsystem Delivers Highest Performance

The RM9000x2 CPU subsystem consists of two E9000 MIPS-64(TM) instruction set compatible cores, both running at 1 GHz. Each core has an optimized cache architecture of high performance L1 data and instruction caches, tightly coupled with 256 KB of joint L2 cache providing a total of 512 KB of coherent L2 cache. The L1 caches are accessed in a single CPU cycle. Access to the L2 cache is a best-in-class 5 CPU cycles, or 5 nanoseconds at 1 GHz core frequency. The dual E9000 cores are connected to each other by a sophisticated processor switch, which enables cache transfers between the CPUs at the core frequency. This high-performance architecture solves multiprocessing's perennial problem of slow data transfers between processors in cache coherent systems by delivering 64 Gbit/s of inter-CPU bandwidth.

To accelerate the multiprocessing capabilities, a five-state cache coherency protocol is used. The five-state MOESI protocol extends the functionality of the standard MESI protocol to permit one processor to access modified data from the other processor's cache. Full hardware I/O coherency is supported over the HyperTransport and SysAD interfaces, enabling I/O devices coherent access to memory without software intervention. The dual CPU cores can run as fully cache coherent symmetric multi-processors (SMP), or completely independent with hardware enforced protection mechanisms. The latter mechanism might be used for separate control plane/data plane processing while the former might be used for separate ingress/egress processing.

Direct Deposit Cache Significantly Increases Packet Processing

Performance

The RM9000x2 features multiple enhancements to its cache architecture that significantly increase packet-processing performance. Direct Deposit Cache provides the ability to write directly into cache over both the HyperTransport and SysAD busses, eliminating costly external memory cycles. In Auto-Deposit operation, the packet header is automatically written into cache, while the payload is written into main memory. Live-Deposit operation provides the ability to dynamically write entire HyperTransport packets into cache. Live-Deposit operation also supports writing directly into cache using Direct Memory Access (DMA). Additional RM9000x2 cache features include Fast Packet Cache, which allows bypassing of L2 cache on a per-page basis and further increases packet-processing performance.

On-Chip I/O Busses Promote Scalability

The integrated high-speed bus interfaces include HyperTransport, DDR SDRAM, SysAD, and a local bus, which provides a boot bus and connectivity to slower speed devices. The RM9000x2 HyperTransport I/O interface is a 500 MHz DDR bus that delivers 16 Gbit/s of raw bus bandwidth for maximum performance and provides connectivity to a wide range of high-speed networking peripherals. The 200 MHz DDR memory controller offers 25.6 Gbit/s of memory bandwidth. Up to four Gigabytes of error correcting code (ECC) protected main memory can be addressed. The SysAD bus enables connectivity to all SysAD-based peripheral devices and delivers a seamless upgrade path for existing RM7000 family designs.

Pricing and Availability

The RM9000x2 dual 1GHz multiprocessor is now available and priced at $350 in 10K units. Evaluation boards are currently available. For a comprehensive support package with datasheets and device models, please visit PMC-Sierra's web site at http://www.pmc-sierra.com/processors or contact applications support at [e-mail].

About PMC-Sierra

PMC-Sierra is a leading provider of high speed broadband communications and storage semiconductors and MIPS-based processors for Enterprise, Access, Metro Optical Transport, Storage Area Networking and Wireless network equipment that makes up the backbone of the Internet. The company offers worldwide technical and sales support, including a network of offices throughout North America, Europe and Asia. The company's quality system is registered with the Quality Management Institute to the ISO 9001 standard. As co-founder of the SATURN(R) Development Group, PMC-Sierra works with over 30 other member companies to PMC-Sierra Samples RM9000x2 64-Bit Dual Gigahertz MIPS-based Multiprocessor with Integrated Memory and I/O Interfaces Page 4/4 define and develop interoperable, standard-compliant solutions for high speed networking applications.

PMC-Sierra is included in the S&P 500 Index which consists of 500 stocks chosen for market size, liquidity, and industry group representation and in the Nasdaq-100 Index (NDX) which contains the largest non-financial companies on the Nasdaq Stock Market. PMC-Sierra is publicly traded on the Nasdaq Stock Market under the PMCS symbol. For more information, visit http://www.pmc-sierra.com.

Attachments

Figure 1: RM9000x2 Block Diagram available at http://www.pmc-sierra.com/pressRoom/pdf/rm9000x2_sampling_fig.pdf

RM9000x2 Photo available at http://www.pmc-sierra.com/pressRoom/photos/index.html

Technical Glossary available at http://www.pmc-sierra.com/pressRoom/glossary.html

(C) Copyright PMC-Sierra, Inc. 2002. All rights reserved. SATURN(R) is a registered trademark of PMC-Sierra, Inc. PMC-Sierra(TM) and RM9000x2(TM) are trademarks of PMC-Sierra, Inc. All other trademarks are the property of the respective owners.