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PMC-Sierra Introduces the Industry's Most Integrated CMOS OC-48c Physical Layer/Framer Device.


Business/High Tech Editors

NOTE: figures and a photo relating to this story will be available

to journalists to download today at www.newstream.com

VANCOUVER, B.C.--(BUSINESS WIRE)--May 4, 2000

The New S/UNI-2488 OC-48c Framer is the First all-CMOS Physical Layer Solution to Integrate Analog Clock and Data Recovery, Clock Synthesis,

Serializer/Deserializer Functions with the Digital Framer

PMC-Sierra (Nasdaq:PMCS) today announced the PM5381 S/UNI-2488 physical layer / framer device, the industry's first complete all-CMOS mixed-signal solution for OC-48c applications.

The S/UNI-2488 device integrates the digital framer and processor functions together with complete analog physical layer front end clock and data recovery, clock synthesis (CRSU) and serializer/deserializer (SERDES) functions (see Figure 1). The low-power, single chip S/UNI-2488 device provides world-class jitter performance, including jitter transfer compliance. The S/UNI-2488 device also provides for a unique high-speed serial-to-serial and serial-to-parallel dual-mode operation which enables the mass deployment of high speed routers, multi-service switches and optical cross-connect equipment (see Figure 2).

Implemented entirely in mainstream 0.18 micron / 1.8 volt CMOS technology, the S/UNI-2488 physical layer / framer achieves a typical power consumption of under 3 watts, which sets the standard relative to alternative multi-chip and/or exotic material PHY/framer approaches. The use of mainstream CMOS for high-speed OC-48 systems enables lower power and ease of future silicon integration for next-generation equipment upgrades.

The S/UNI-2488 leverages PMC-Sierra's extensive high-speed, CMOS analog design expertise developed previously at OC-3c (155 Mbit/s) and OC-12c (622 Mbit/s) rates. The OC-48c (2.5 Gbit/s) physical layer front end CRSU and SERDES functions implement analog phase-locked-loop circuit technology that meets Bellcore GR-253 intrinsic jitter specifications as well as meeting jitter tolerance and jitter transfer specifications.

Analog Serial-to-Serial OC-48 Channelized Refers to an architecture that transmits data in channels. It often refers to the 64 Kbps channels in T1 lines, which were originally developed to handle digitized voice streams (TDM). See TDM.  Operating Mode

The S/UNI-2488 device provides a unique analog serial backplane port for optical cross-connect applications and/or automatic protection switching (APS) line card redundancy where packet or cell termination is not required. Previously, individual DWDM lambdas were only able to provision a single user service. With its analog serial backplane port, the S/UNI-2488 connects seamlessly to the PM5372 TSE See Tokyo Stock Exchange.

TSE

1. See Tokyo Stock Exchange (TSE).

2. See Toronto Stock Exchange (TSE).
 device providing for bit-synchronous STS-1 optical cross connect grooming. Now each individual DWDM lambda can be fully provisioned to carry multiple user services, greatly enhancing carrier service deployment (see Figure 3).

Standards Compliant to POS-PHY Level 3 and UTOPIA Level 3 Backplanes

The OC-48c S/UNI-2488 in serial-to-parallel digital framer mode acts as the second device introduced in PMC-Sierra's Packet-over-SONET/SDH Level 3 (POS-PHY Level 3) family, following the PM7390 S/UNI-MACH48 device of the CHESS(TM) OC-48 chip set. Its 32-bit x 104 MHz (3.2 Gbit/s) backplane interface can be configured in either standard compliant POS-PHY Level 3 mode for simultaneous streaming packet and cell transfer or standard compliant UTOPIA Level 3 mode for dedicated cell-only transfer (see Figure 4). In this manner, the S/UNI-2488 can be utilized for a wide-range of multi-service, data-link and/or ATM Layer system termination applications.

"POS-PHY Level 3 meets our needs in supporting both packets and cells between different link layer and PHY layer devices," said Michael Takefman, manager of hardware engineering for the optical internetworking business unit of Cisco Systems. "That is why we selected POS-PHY Level 3 as the interface between the OC-48 POS/ATM Framer and SRP SRP - A data link layer protocol.  (Spatial Reuse Protocol Spatial Reuse Protocol is a networking protocol developed by Cisco. It is a MAC-layer (sublayer of layer 2) protocol for ring-based packet internetworking, submitted to the IEEE 802.17 Resilient Packet Ring (RPR) Working Group for consideration as a standard. ) Media Access Controller on the OC-48 line card for the Cisco GSR-12000 platform."

The POS-PHY Level 3 system interface was standardized by the SATURN(R) Development Group in December 1998, and is publicly available at www.pmc-sierra.com/posphylevel3. The interface specification is balloting at both the Optical Internetworking Forum The Optical Internetworking Forum (OIF) was organized to facilitate and accelerate the development of next-generation optical internetworking products. The OIF produces Electrical, Tunable Laser, Very Short Reach Hardware Interfaces.  and the ATM Forum, providing an industry-wide standard for transferring packets and cells between networking integrated circuits.

"The recent CHESS OC-48 chip set and today's S/UNI-2488 OC-48c product announcements, along with last quarter's acquisition of AANetcom are further advances in PMC-Sierra's strategy to enable optical carrier-class service provisioning equipment optimized for DWDM and SONET/SDH transport technologies" said Steve Perna, vice president and general manager of PMC-Sierra's Optical Networking Division.

Pricing, Availability and Customer Support

The S/UNI-2488 is packaged in a 31mm by 31mm 416 UBGA package, representing the smallest footprint available. It is priced at $269 in 1KU volume quantities, with samples available in July. A comprehensive support package including reference designs, software drivers and bus functional models will simplify design and reduce time to market. The reference design and software drivers will be featured on PMC-Sierra's web site at http://www.pmc-sierra.com and the bus functional model may be requested through apps@pmc-sierra.com.

About PMC-Sierra

PMC-Sierra's extensive family of broadband communication semiconductors is enabling the equipment that makes up the backbone of the Internet. The company develops Internet Protocol (IP), ATM, SONET/SDH, T1/E1 and T3/E3 solutions for wide area network and Internet infrastructure equipment. PMC-Sierra's quality system is registered with the Quality Management Institute to the ISO (1) See ISO speed.

(2) (International Organization for Standardization, Geneva, Switzerland, www.iso.ch) An organization that sets international standards, founded in 1946. The U.S. member body is ANSI.
 9001 standard. As co-founder of the SATURN(R) Development Group, PMC-Sierra works with over 30 other member companies to define and develop interoperable, standard-compliant solutions for high speed networking applications.

PMC-Sierra offers worldwide technical and sales support including a network of offices throughout North America, Europe and Asia. PMC-Sierra is publicly traded on the Nasdaq Stock Market Nasdaq stock market

The first electronic stock market listing over 5000 companies. The Nasdaq stock market comprises two separate markets, namely the Nasdaq National Market, which trades large, active securities and the Nasdaq Smallcap Market that trades emerging growth companies.
 under the symbol "PMCS". The company is included in the Nasdaq-100 Index (NDX) which contains the largest non-financial companies on the Nasdaq Stock Market. The Nasdaq-100 Index is the benchmark for the Nasdaq-100 Index Tracking Stock (AMEX AMEX

See: American Stock Exchange
:QQQ QQQ

The Nasdaq-100 Index Tracking Stock. This is a tracking stock which trades like an index mutual fund which follows the Nasdaq 100 index. It trades continuously.


QQQ 
). For more information about PMC-Sierra, visit http://www.pmc-sierra.com.

Attachments NOTE: The following figures relating to this story will be available to journalists to download today at www.newstream.com

Figure 1: S/UNI-2488 High Level Block Diagram Figure 2: S/UNI-2488 for OC-48c MAN/Edge WAN Applications Figure 3: 40Gbit/s Cross-Connect Card in an Optical Switch Application

Utilizing S/UNI-2488 and TSE Figure 4: S/UNI-2488 Dual-Mode Operation Photo:

S/UNI-2488 OC-48c physical layer/framer device

Technical Glossary

APS Automatic Protection Switching ATM Asynchronous Transfer Mode See ATM.

(communications) Asynchronous Transfer Mode - (ATM, or "fast packet") A method for the dynamic allocation of bandwidth using a fixed-size packet (called a cell).

See also ATM Forum, Wideband ATM.

ATM acronyms.

Indiana acronyms.
 CHESS Channelizer Engine for SONET/SDH CMOS Complementary Metal Oxide Semiconductor See CMOS.

(integrated circuit) Complementary Metal Oxide Semiconductor - (CMOS) A semiconductor fabrication technology using a combination of n- and p-doped semiconductor material to achieve low power dissipation.
 CRSU Clock and Data Recovery and Clock Synthesis Unit DWDM Dense Wavelength Division Multiplexing See WDM.  LAMBDA Lambda is used as the symbol for wavelength in

lightwave systems LVDS Low Voltage Differential (hardware) Low Voltage Differential - (LVD) A method of driving SCSI cables that will be formalised in the SCSI-3 specifications. LVD uses less power than the current differential drive (HVD), is less expensive and will allow the higher speeds of Ultra-2 SCSI. LVD requires 3.  Signalling MAN

Metropolitan Area Network OC Optical Carrier POS (1) See point of sale and packet over SONET.

(2) "Parent over shoulder." See digispeak.

POS - point of sale
 

Packet-over-SONET/SDH PHY Physical Layer POS-PHY

Level 3 interface defines operations between

Physical Layer Devices (such as ATM, POS and GigE

framers) and Link Layer devices (such as ATM, IP and

GigE forwarding devices) at OC-48 line rates SATURN PMC-Sierra works with other companies to define and

develop interoperable, standard-compliant solutions

for high speed networking applications SDH (Synchronous Digital Hierarchy) The European counterpart to SONET. See SONET.

SDH - Synchronous Digital Hierarchy
 Synchronous Digital Hierarchy (communications, standard) Synchronous Digital Hierarchy - (SDH) An international digital telecommunications network hierarchy which standardises transmission around the bit rate of 51.84 megabits per second, which is also called STS-1.  - the European

counterpart to SONET SERDES Serializer/Deserialize SONET

Synchronous Optical NETwork (networking) Synchronous Optical NETwork - (SONET) A broadband networking standard based on point-to-point optical fibre networks. SONET will provide a high-bandwidth "pipe" to support ATM-based services.  SRP Spatial Reuse Protocol STM (Scanning Tunneling Microscope) A microscope that can image down to the atomic level. An STM uses a piezoelectric tube with a tiny sharp tip at the end that is moved within nanometers of the object being sampled.  

Synchronous Transport Module STS (Synchronous Transport Signal) The electrical equivalent of the SONET optical signal. In SDH, the European counterpart of SONET, STS is known as STM (Synchronous Transport Module).   Sychronous Transport Signal UBGA Ultra Ball Grid Array “BGA” redirects here. For other uses, see BGA (disambiguation).

A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits.
 UTOPIA Universal Test & Operations PHY Interface for ATM WAN Wide Area Networks

(c)Copyright PMC-Sierra, Inc. 2000. All rights reserved. SATURN(R)and S/UNI(R)are registered trademarks of PMC-Sierra, Inc. PMC-Sierra(TM), POS-PHY Level 3(TM), S/UNI-2488(TM), and CHESS(TM)are trademarks of PMC-Sierra, Inc.
COPYRIGHT 2000 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2000, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Geographic Code:1CANA
Date:May 4, 2000
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