PMC-Sierra Introduces New OC-48 Chip Set Architecture to Enable Next Generation Optical Network Deployment.Business/Hi-Tech Editors NOTE: A PHOTO, FIGURES and TABLES relating to this story will be available to journalists to download today at www.newstream.com VANCOUVER, B.C.--(BUSINESS WIRE)--April 24, 2000 The CHESS(TM) Channelized Refers to an architecture that transmits data in channels. It often refers to the 64 Kbps channels in T1 lines, which were originally developed to handle digitized voice streams (TDM). See TDM. Chip Set Architecture Manages and Grooms Multi-service IP, Voice, Frame Relay and ATM Traffic Over Both SONET/SDH and DWDM Transport Equipment PMC-Sierra (Nasdaq:PMCS) today announced a new OC-48/OC-48c (2.5 Gbit/s) channelized architecture designed to completely revolutionize the way carrier and Internet Service Provider Internet service provider (ISP) Company that provides Internet connections and services to individuals and organizations. For a monthly fee, ISPs provide computer users with a connection to their site (see data transmission), as well as a log-in name and password. (ISP) networks are built, deployed and managed. The CHESS (Channelizer Engine for SONET/SDH) chip set will allow for convergence of traditionally separate voice and data infrastructure into new, highly integrated carrier-class multi-service networks. The CHESS chip set is the industry's first and only chip set architecture allowing IP Routing, ATM/Frame Relay Switching, SONET/SDH digital cross connect/add-drop multiplexing and Dense Wavelength Division Multiplexing See WDM. (DWDM) transport functionality to be built in a single, space-efficient hardware platform. By replacing as many as five or six older, discrete network equipment elements, multi-service equipment networks utilizing the CHESS chip set will enable carriers and ISPs to provision a greater number of services more dynamically and at lower cost than ever before (see Figure 1). The CHESS chip set manages scarce SONET/SDH bandwidth and DWDM lambda wavelengths which are critical to the effective deployment and operation of true multi-service networks realizing "Any-Service, Any-User, Any-Channel". These networks can now utilize simplified software management layers making them significantly easier for carriers and ISPs to operate. The CHESS Chip Set Upgrades MANs and Edge WANs Which Are Critical to Carrier Business Growth Carriers are urgently upgrading their infrastructure in emerging, high-growth Metropolitan Area Network (MAN) and edge Wide Area Network (WAN) regions to maintain and grow a very lucrative Service Level Agreement (SLA) provisioning business. These networks are ideally suited for SONET/SDH fiber backbones due to its scalability, availability and reliability. They are, however, highly under-utilized with the current OC-3/STM-1 (155 Mbit/s) and OC-12/STM-4 (622 Mbit/s) rate operation. The availability of the CHESS chip set provides an immediate upgrade path to OC-48/OC-48c/STM-16 (2.5 Gbit/s) rate operation. The CHESS chip set can also scale beyond 2.5 Gbit/s rate applications to support future OC-192/STM-64 applications running at 10Gbit/s rates. The CHESS Chip Set Creates Next Generation, Carrier-Class, Multi-Service and Optical Equipment The edge of the network is a very challenging environment for a carrier or ISP to manage. MAN and edge WAN networks must not only aggregate the multi-protocol, low- and multi-rate DS0 (64 Kbit/s) to DS3 (45 Mbit/s) traffic from access customer premise regions, but are now also required to aggregate the wavelength lambda base rate of OC-48/OC-48c (2.5 Gbit/s) traffic from native DWDM transport networks. To meet these difficult requirements it is necessary to manage and groom SONET/SDH traffic at both STS-1/DS3 (51/45 Mbit/s) base access rate and at OC-48/STM-16 (2.5 Gbit/s) base DWDM rate granularities. The CHESS chip set is the first and only industry chip set to provide capability for such dual-rate SONET/SDH grooming capability. The CHESS chip set provides SONET/SDH framing capability at each of the key OC-3, OC-12 and OC-48 optical line rates. Its STS-1 channelized traffic grooming capability allows for the development of dedicated service processing cards such as Packet-over-SONET, ATM and Frame Relay that replace entire, dedicated network service equipment utilized previously (see Figure 2 and Figure 3). But perhaps most importantly, the STS-1 grooming capability of the CHESS chip set will allow for sub-lambda wavelength processing such that multiple user services can be run over individual 2.5 Gbit/s lambda wavelengths (see Figure 4). This solves the optimal lambda utilization problem of provisioning more than a single user service per lambda and will help enable the creation of new multi-service optical equipment classes such as the integration of cross connects, add-drop multiplexers and switches. "As the initial offering in our OC-48 strategy, the CHESS chip set architecture unveiling is a highly anticipated event for PMC-Sierra," said Steve Perna, PMC-Sierra's vice president and general manager, Optical Networking Division. "In conjunction with our key strategic customers, we have focused over the last 15 months on developing an OC-48 Internet Service Provider architecture that leverages significant system level expertise designed to optimize the scarce resources of network bandwidth, lambda wavelength and equipment form factor. The CHESS chip set architecture will significantly improve the ability of our customers to provide increased service level provisioning in their next-generation carrier-class equipment," he concluded. Pricing, Packaging and Customer Support The CHESS chip set architecture consists of five devices, each by itself unique in the industry for its high density and functionality, designed to operate seamlessly together (See Table 1). -- SPECTRA-2488: OC-48/OC-48c/STM-16 and 4xOC-12/STM-4 SONET/SDH framer with STS-1/AU3 channelizer -- SPECTRA-4x155: 4xOC-3/STM-1 SONET/SDH framer with STS-1/AU3 channelizer -- TelecomBus Serializer (TBS): STS-48/STM-16 LVDS serializer and Auto Protection Switching (APS) tri-port -- Transmission Switch Element (TSE See Tokyo Stock Exchange. TSE 1. See Tokyo Stock Exchange (TSE). 2. See Toronto Stock Exchange (TSE). ): 768 channel STS-1/AU3 cross connect traffic groomer (40Gbit/s capacity) -- S/UNI-MACH48: 48-channel Packet-Over-SONET Processor and ATM Cell processor with 48 channel STS-1 to DS3 asynchronous Refers to events that are not synchronized, or coordinated, in time. The following are considered asynchronous operations. The interval between transmitting A and B is not the same as between B and C. The ability to initiate a transmission at either end. mapper The SPECTRA-2488, TBS, TSE, and S/UNI-MACH48 are implemented in low power 0.18 micron CMOS technology, and the SPECTRA-4x155 in 0.35 micron CMOS. The PM5315/SPECTRA-2488 and PM5316/SPECTRA-4x155 are both packaged in 520 SBGA, the PM5310/TelecomBus Serializer (TBS) is packaged in 352 UBGA, and both the PM5372/Transmission Switch Element (TSE) and PM7390/S/UNI-MACH48 are packaged in 560 UBGA. Pricing in volume quantities is $99 for the PM5310/TBS, $324 for the PM5316/SPECTRA-4x155, $395 for the PM5315/SPECTRA-2488, $396 for the PM7390/S/UNI-MACH48 and $499 for the PM5372/TSE. PM5310/TBS and PM5372/TSE will be available as early as May 2000. Other samples will be available in the subsequent months. The CHESS chip set data sheets and technical overview are available on PMC-Sierra's web site at: http://www.pmc-sierra.com/chess. About PMC-Sierra PMC-Sierra's extensive family of broadband communication semiconductors is enabling the equipment that makes up the backbone of the Internet. The company develops Internet Protocol (IP), ATM, SONET/SDH, T1/E1 and T3/E3 solutions for wide area network and Internet infrastructure equipment. PMC-Sierra's quality system is registered with the Quality Management Institute to the ISO (1) See ISO speed. (2) (International Organization for Standardization, Geneva, Switzerland, www.iso.ch) An organization that sets international standards, founded in 1946. The U.S. member body is ANSI. 9001 standard. As co-founder of the SATURN(R) Development Group, PMC-Sierra works with over 30 other member companies to define and develop interoperable, standard-compliant solutions for high speed networking applications. PMC-Sierra offers worldwide technical and sales support including a network of offices throughout North America, Europe and Asia. The company is publicly traded on the Nasdaq Stock Market Nasdaq stock market The first electronic stock market listing over 5000 companies. The Nasdaq stock market comprises two separate markets, namely the Nasdaq National Market, which trades large, active securities and the Nasdaq Smallcap Market that trades emerging growth companies. under the symbol "PMCS". PMC-Sierra is included in the Nasdaq-100 Index (NDX) which contains the largest non-financial companies on the Nasdaq Stock Market. The Nasdaq-100 Index is the benchmark for the Nasdaq-100 Index Tracking Stock (AMEX AMEX See: American Stock Exchange :QQQ QQQ The Nasdaq-100 Index Tracking Stock. This is a tracking stock which trades like an index mutual fund which follows the Nasdaq 100 index. It trades continuously. QQQ ). For more information about PMC-Sierra, visit http://www.pmc-sierra.com. Attachments Technical Glossary Figure 1: CHESS Chip Set Consolidates Older Equipment into a Single, Multi-Service Platform Figure 2: CHESS Chip Set Architecture Figure 3: CHESS Chip Set Integrates Multiple Equipment Functions into Dedicated Card Designs Figure 4: CHESS Chip Set Sub-Lambda Wavelength Processing Capability Grooms DWDM Traffic into IP, ATM and TDM (Time Division Multiplexing) A technology that transmits multiple signals simultaneously over a single transmission path. Each lower-speed signal is time sliced into one high-speed transmission. Services Table 1: CHESS Chip Set Architecture Device Details Photo Technical Glossary ATM Asynchronous Transfer Mode See ATM. (communications) Asynchronous Transfer Mode - (ATM, or "fast packet") A method for the dynamic allocation of bandwidth using a fixed-size packet (called a cell). See also ATM Forum, Wideband ATM. ATM acronyms. Indiana acronyms. APS Automatic Protection Switching AU Administrative Unit CHESS Channelizer Engine for SONET/SDH CMOS Complimentary Metal Oxide Semiconductor See MOS. (electronics) Metal Oxide Semiconductor - (MOS) The three materials used to form a gate in the most common kind of Field Effect Transistor - a MOSFET. DS Digital Signal DSLAM Digital Subscriber Line Access Multiplexer A Digital Subscriber Line Access Multiplexer (DSLAM) allows telephone lines to make faster connections to the Internet. It is a network device, located near the customer's location, that connects multiple customer Digital Subscriber Lines (DSLs) to a high-speed Internet DWDM Dense Wavelength Division Multiplexing FR Frame Relay HDLC High-level Data Link Control (networking) High-level Data Link Control - (HDLC) A general-purpose data link control protocol defined by ISO for use on both point-to-point and multipoint (multidrop) data links. It supports full-duplex, transparent-mode operation. IP Internet Protocol LVDS Low Voltage Differential (hardware) Low Voltage Differential - (LVD) A method of driving SCSI cables that will be formalised in the SCSI-3 specifications. LVD uses less power than the current differential drive (HVD), is less expensive and will allow the higher speeds of Ultra-2 SCSI. LVD requires 3. Signalling MAN Metropolitan Area Network MUX Multiplexer OC Optical Carrier POS (1) See point of sale and packet over SONET. (2) "Parent over shoulder." See digispeak. POS - point of sale Packet-Over-SONET SBGA Super Ball Grid Array “BGA” redirects here. For other uses, see BGA (disambiguation). A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. SDH (Synchronous Digital Hierarchy) The European counterpart to SONET. See SONET. SDH - Synchronous Digital Hierarchy Synchronous Digital Hierarchy (communications, standard) Synchronous Digital Hierarchy - (SDH) An international digital telecommunications network hierarchy which standardises transmission around the bit rate of 51.84 megabits per second, which is also called STS-1. - the European counterpart to SONET SLA Service Level Agreement SONET Synchronous Optical NETwork (networking) Synchronous Optical NETwork - (SONET) A broadband networking standard based on point-to-point optical fibre networks. SONET will provide a high-bandwidth "pipe" to support ATM-based services. STM (Scanning Tunneling Microscope) A microscope that can image down to the atomic level. An STM uses a piezoelectric tube with a tiny sharp tip at the end that is moved within nanometers of the object being sampled. Synchronous Transport Module STS Sychronous Transport Signal TBS TelecomBus Serializer TDM Time Division Multiplexing (communications) time division multiplexing - (TDM) A type of multiplexing where two or more channels of information are transmitted over the same link by allocating a different time interval ("slot" or "slice") for the transmission of each channel. I.e. TSE Transmission Switch Element UBGA Ultra Ball Grid Array VT/TU SONET Virtual Tributaries/SDH Tributary Units (c)Copyright PMC-Sierra, Inc. 2000. All rights reserved. SATURN(R)and S/UNI(R)are registered trademarks of PMC-Sierra, Inc. PMC-Sierra(TM), SPECTRA(TM)and CHESS(TM)are trademarks of PMC-Sierra, Inc. |
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