PMC-Sierra Introduces Highest Performance Multilink T1/E1 Packet Processing for a Channelized OC-12 in a Single Chip.
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BURNABY, British Columbia--(BUSINESS WIRE)--March 5, 2001
New FREEDM FREEDM Frame Engine and Data Link Manager (TM) Products Provide 4 Times Density Improvement for
PMC-Sierra (Nasdaq:PMCS) today announced two new members of its FRame Engine and Datalink Manager (FREEDM(TM)) packet processor family: the PM7388 FREEDM-336A1024 and the PM7389 FREEDM-84A1024.
The FREEDM-336 is the industry's first packet processor to support up to 336 T1 lines and achieve a sustained wire speed throughput for short IP packets. The FREEDM-336 also supports up to 252 E1 links and is ideal for channelized Refers to an architecture that transmits data in channels. It often refers to the 64 Kbps channels in T1 lines, which were originally developed to handle digitized voice streams (TDM). See TDM. nxOC-12 and OC-48 port card designs in edge routers, optical access equipment and multiservice switches (Figure 1). The FREEDM-84 supports up to 84 T1 or 63 E1 links over 1024 HDLC channels and is ideal for nxDS3 and nxOC-3 port card designs. By integrating a dedicated multilink packet processor engine, the new FREEDM devices provide greater than 4 times the density achievable with previous CPU CPU
in full central processing unit
Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. and FPGA solutions.
Multilink Technology Bridges the Bandwidth Gap between T1/E1 and T3/E3
The explosive demand for high data rate applications is pushing the WAN bandwidth requirement for many business users beyond the capability of a single T1/E1 link. The next service level above T1's 1.544 Mbit/s is a large jump to the 45 Mbit/s T3 that has limited deployment in the access network and may not offer users with the bandwidth relief at the target price point. Multilink Point-to-Point Protocol (ML-PPP ML-PPP Multi-Link Point-To-Point Protocol ) and Multilink Frame Relay (ML-FR) are standard compliant solutions designed to bridge the bandwidth gap between T1/E1 and T3/E3 by supporting dynamic bandwidth allocation Dynamic Bandwidth Allocation (DBA) is a technique by which traffic bandwidth in a shared telecommunications medium can be allocated on demand and fairly between different users of that bandwidth. in multiple T1/E1 rates.
Early implementations of ML-PPP and ML-FR relied on large and complex FPGA, ASIC, or processor-based implementations. Network system architects can now leverage the standard compliant ML-PPP and ML-FR capabilities of the new FREEDM products to develop a single design that support rates ranging from DS0, T1/E1, multilink T1/E1 bundles to unchannelized DS3, at greater than 4 times the density than previously achievable (Figures 2 and 3).
"PMC-Sierra's commitment to lead the industry in highly channelized packet processor solutions is critical for us to deliver the necessary port density in our next generation ERX-1400 Edge Routing Switches," said Kurt Melden, chief technology officer at Unisphere Networks. "The density improvement provided by FREEDM-336 allows us to meet the large scale demands for edge-enabled services," concluded Melden.
The FREEDM-336 and FREEDM-84 expand PMC-Sierra's multiservice architecture. Together, with PMC-Sierra's SPECTRA(TM) (SONET), S/UNI(R)-IMA (ATM inverse multiplexor), TEMUX (AAL1 voice-over-ATM), AAL1gator(TM) (voice-over-IP/ATM processor) and MECA(TM) product families, a single design can support all of the major protocols at the edge of the network (Figure 4). This chip set satisfies the physical and power constraints found in the newest edge router and switch equipment. A complete channelized OC-48 or 4xOC-12 solution requires only a single SPECTRA-2488, 16 TEMUX-84s and 4 FREEDM-336s. Such designs can be rapidly brought to production by applying the software and hardware knowledge gained from the hundreds of previous generation designs based on the FREEDM family (Figure 5).
"Leveraging the ubiquitous copper access infrastructure is a major initiative of service providers today," said Glenn Bindley, general manager and vice president of PMC-Sierra's Access Product Division. "By incorporating Multilink technologies, the FREEDM-336 and FREEDM-84 provide unprecedented line card functionality and densities for next generation IP routers and optical switches," concluded Bindley.
Pricing, Availability and Customer Support
The FREEDM-336 and FREEDM-84 devices are packaged in a 40 x 40 mm2, 520 pin SBGA package. The FREEDM-336 is priced at $1668 in 1KU quantities through distribution. The FREEDM-84 is priced at $575 in 1KU quantities through distribution. Both chips are low-power 1.8V CMOS devices rated for industrial temperature range operation (-40 to +85 degrees Celsius) and are sampling in Q2, 2001. A comprehensive support package including datasheets, software drivers, user manual, hardware reference designs, device models and a technical overview is available on PMC-Sierra's web site at http://www.pmc-sierra.com.
PMC-Sierra is accelerating the broadband revolution. PMC-Sierra's extensive family of broadband communication semiconductors enables the equipment that makes up the backbone of the Internet. PMC-Sierra offers worldwide technical and sales support including a network of offices throughout North America, Europe and Asia. PMC-Sierra is publicly traded on the Nasdaq Stock Market Nasdaq stock market
The first electronic stock market listing over 5000 companies. The Nasdaq stock market comprises two separate markets, namely the Nasdaq National Market, which trades large, active securities and the Nasdaq Smallcap Market that trades emerging growth companies. under the symbol "PMCS". The company is included in the Nasdaq-100 Index (NDX) which contains the largest non-financial companies on the Nasdaq Stock Market. The Nasdaq-100 Index is the benchmark for the Nasdaq-100 Index Tracking Stock (Amex:QQQ QQQ
The Nasdaq-100 Index Tracking Stock. This is a tracking stock which trades like an index mutual fund which follows the Nasdaq 100 index. It trades continuously.
PMC-Sierra develops Internet Protocol (IP), ATM, SONET/SDH, T1/E1, T3/E3, Voice-over-Packet, wireless infrastructure, MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. (TM) microprocessor, and Gigabit Ethernet solutions for wide area network (WAN), and Internet networking equipment. The company's quality system is registered with the Quality Management Institute to the ISO (1) See ISO speed.
(2) (International Organization for Standardization, Geneva, Switzerland, www.iso.ch) An organization that sets international standards, founded in 1946. The U.S. member body is ANSI. 9001 standard. As co-founder of the SATURN(R) Development Group, PMC-Sierra works with over 30 other member companies to define and develop interoperable, standard-compliant solutions for high speed networking applications. For more information about PMC-Sierra, visit http://www.pmc-sierra.com.
Attachments Figure 1: OC-48 Port Card Figure 2
and 3: OC-12 Density Improvement - Currently Available Solution
OC-12 Density Improvement - PMC-Sierra Solution Figure 4: Complete Any Service, Any Port Solution Figure 5: FREEDM Product Family Photo Technical Glossary
AAL1gator(TM) ATM Adaptation Layer 1 SAR (Segmentation And Reassembly) The protocol that converts data to cells for transmission over an ATM network. It is the lower part of the ATM Adaption Layer (AAL), which is responsible for the entire operation. See AAL.
SAR - segmentation and reassembly Processor
ATM Asynchronous Transfer Mode See ATM.
(communications) Asynchronous Transfer Mode - (ATM, or "fast packet") A method for the dynamic allocation of bandwidth using a fixed-size packet (called a cell).
See also ATM Forum, Wideband ATM.
CMOS Complimentary Metal Oxide Semiconductor See MOS.
(electronics) Metal Oxide Semiconductor - (MOS) The three materials used to form a gate in the most common kind of Field Effect Transistor - a MOSFET.
CPU Central Processing Unit See CPU.
(architecture, processor) central processing unit - (CPU, processor) The part of a computer which controls all the other parts. Designs vary widely but the CPU generally consists of the control unit, the arithmetic and logic unit (ALU), registers, temporary buffers
DS Digital Signal
E1, E2, E3 European (world) standards for 2.048 Mbit/s,
8.448 Mbit/s, and 34.368 Mbit/s
FPGA Field Programmable Gate Array See FPGA.
FREEDM(TM) FRame Engine and Datalink Manager
H-MVIP High-capacity Multi Vendor Integration Protocol
HDLC High Level Data Link Control
IP Internet Protocol
LIU Line Interface Unit
Mbit/s One million bits per second
MECA(TM) Multiprocessor Embedded Communications
MIPS(TM) Million Instructions Per Second Noun 1. million instructions per second - (computer science) a unit for measuring the execution speed of a computer's CPU (but not the whole system); "4 MIPS is 4,000,000 instructions per second"
ML-FR Multilink Frame Relay
ML-PPP Multilink Point-to-Point Protocol
OC-12 Optical Carrier 12 (622 Mbit/s)
OC-48 Optical Carrier 48 (2488 Mbit/s)
SATURN(R) PMC-Sierra works with over 30 member
companies to define and develop
solutions for high speed networking
SBGA Super Ball Grid Array “BGA” redirects here. For other uses, see BGA (disambiguation).
A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits.
SBI Scaleable Bandwidth Interconnect
SDH (Synchronous Digital Hierarchy) The European counterpart to SONET. See SONET.
SDH - Synchronous Digital Hierarchy Synchronous Digital Hierarchy (communications, standard) Synchronous Digital Hierarchy - (SDH) An international digital telecommunications network hierarchy which standardises transmission around the bit rate of 51.84 megabits per second, which is also called STS-1. . Worldwide
standard for synchronous transmission systems
(typically fiber optic). Similar to SONET
SERDES 10-bit Serializer/Deserializer physical-medium
attachment sub-layer for Gigabit Ethernet
SPECTRA(TM) SONET/SDH Payload Extractor/Aligner
SPECTRA(TM)-2488 SONET/SDH Payload Extractor/Aligner for
SPECTRA(TM)-622 SONET/SDH Payload Extractor/Aligner for
SONET Synchronous Optical Network (networking) Synchronous Optical NETwork - (SONET) A broadband networking standard based on point-to-point optical fibre networks. SONET will provide a high-bandwidth "pipe" to support ATM-based services. . North American
standard for synchronous transmissions systems
(typically fiber optic). See also SDH
S/UNI(R)-IMA SATURN User Network Interface Inverse
Multiplexer for ATM (IMA (Interactive Multimedia Association, Annapolis, MD) An earlier trade association founded in 1988 originally as the Interactive Video Industry Association. It provided an open process for adopting existing technologies and was involved in subjects such as networked services, scripting )
T1 North American standard for 1.544 Mbit/s
T3 North American standard for a TDM (Time Division Multiplexing) A technology that transmits multiple signals simultaneously over a single transmission path. Each lower-speed signal is time sliced into one high-speed transmission.
digital channel carrier that operates
at 44.736 Mbit/s. It can multiplex 28
DS-1 signals and is synonymous with
TEMUX High Density T1/E1 Framer with Integrated VT/TU
Mapper and M13 Multiplexer
UTOPIA Universal Test and Operation Physical Interface
for ATM. Physical layer specification for
local connectivity between ATM devices
VoX Voice Operated eXchange
VT Mapper Virtual Tributary Mapper
WAN Wide Area Network
(c)Copyright PMC-Sierra, Inc. 2001. All rights reserved. S/UNI(R)and SATURN(R)are registered trademarks of PMC-Sierra, Inc. AAL1gator(TM), FREEDM(TM), MECA(TM), SPECTRA(TM)and PMC-Sierra(TM)are trademarks of PMC-Sierra, Inc. MIPS(TM) is a trademark of MIPS Technologies, Inc.
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