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PMC-SIERRA ANNOUNCES INDUSTRY'S FIRST DUAL PORT GIGABIT ETHERNET CHIP WITH POS-PHY LEVEL 3 INTERFACE.


PMC-Sierra (Nasdaq:PMCS PMCS PMC Sierra (stock symbol)
PMCS Project Management Control System
PMCS partial mission-capable, supply (US DoD)
PMCS Preventive Maintenance Checks & Services
PMCS Professional Military Comptroller School
) has announced the PM3386 S/UNI-2xGE dual port Gigabit Ethernet transceiver, the industry's first integrated dual Serializer/Deserializer (SERDES See serializer/deserializer. ) and Gigabit Media Access Control (MAC) controller with the industry standard POS-PHY Level 3 system interface.

The high density S/UNI-2xGE connects directly to optical modules, offers a standard Gigabit Media Independent Interface (GMII GMII Gigabit Media Independent Interface ) and operates at low power levels. By leveraging the POS-PHY Level 3 interface, the S/UNI-2xGE enables the development of Gigabit Ethernet line cards used in carrier class networking equipment. The new chip gives system developers substantial design flexibility, speeds time-to-market, and reduces the overall cost of developing Internet Protocol core and edge routers, multi-service switching platforms (MSSPs), and optical networking products.

The small 27 mm x 27 mm S/UNI-2xGE chip is implemented entirely in mainstream 0.18 micron 3.3 / 1.8 volt CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes.  technology, provides reduced power consumption and simplified silicon integration. Its power consumption is less than 2 watts/port, which offers up to a 60% power savings over low density Gigabit Ethernet implementations that uses discrete SERDES, Gigabit Ethernet MAC and FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market.  devices. With all of these features on one chip, the S/UNI-2xGE device replaces up to six chips.

The S/UNI 2xGE device provides an expedient way to integrate Gigabit Ethernet into multi-service architectures supporting Asynchronous Transfer Mode See ATM.

(communications) Asynchronous Transfer Mode - (ATM, or "fast packet") A method for the dynamic allocation of bandwidth using a fixed-size packet (called a cell).

See also ATM Forum, Wideband ATM.

ATM acronyms.

Indiana acronyms.
 (ATM), Frame Relay (FR), Internet Protocol (IP), and Gigabit Ethernet (GE) traffic at 51 Mbits/s up to 2.5 Gbit/s (OC-48) line rates. With the integration of the POS-PHY Level 3 interface the S/UNI 2xGE does not require glue logic to connect to higher layer devices.

The POS-PHY Level 3 system interface was developed by the SATURN(R) Development Group in December 1998, and is publicly available at http://www.pmc-sierra.com/posphylevel3. This interface specification, in balloting at the Optical Internetworking Forum The Optical Internetworking Forum (OIF) was organized to facilitate and accelerate the development of next-generation optical internetworking products. The OIF produces Electrical, Tunable Laser, Very Short Reach Hardware Interfaces.  and recently ratified by the ATM Forum, provides an industry-wide standard for multi-service system interfaces. POS-PHY Level 3 is the industry standard for 2.5 Gbit/s OC-48 and multi-channel 622-Mbit/s OC-12 transmission rates required by the new generation of super routers and layer 3 switches for multi-service voice and data networks. An interface based on this standard is flexible enough to support not only high-speed Packet-over-SONET (POS (1) See point of sale and packet over SONET.

(2) "Parent over shoulder." See digispeak.

POS - point of sale
) Internet traffic, but Gigabit Ethernet and Asynchronous Transfer Mode (ATM) applications as well.

The S/UNI-2xGE is packaged in a 27 mm by 27 mm, 352 UBGA package. It is priced at $259 in volume quantities, with samples available in November 2000. A comprehensive support package including reference designs, software drivers, application notes, and bus functional models will simplify design and reduce time to market.
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Comment:PMC-SIERRA ANNOUNCES INDUSTRY'S FIRST DUAL PORT GIGABIT ETHERNET CHIP WITH POS-PHY LEVEL 3 INTERFACE.
Publication:EDP Weekly's IT Monitor
Article Type:Product Announcement
Geographic Code:1USA
Date:Oct 9, 2000
Words:441
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