PLX TECHNOLOGY INTRODUCES POWERFUL NEW ADAPTIVE SWITCH FABRIC ARCHITECTURE.

PLX Technology, Inc. has announced its powerful new PLX Adaptive Switch Fabric Architecture that provides the communications infrastructure with unprecedented high availability, scalability and preservation of investment. The PLX Adaptive Switch Fabric Architecture enables Peripheral Component Interconnect (PCI)-based telecommunications, data communications and embedded systems to incorporate 224 PCI bus segments, aggregate tens of gigabits per second, and direct connection of two adjacent PCI devices on the fabric up to 15 feet away, via a high-performance link.

PLX is developing silicon controllers based on this new architecture -- the first switch fabric controllers optimized for edge-access communications equipment such as digital subscriber line access multiplexors (DSLAM), media access gateways and wireless base stations. This 100 percent PCI-compatible silicon will be introduced in early Q1 2001, with volume shipments scheduled for the first half of the year.

Leading communication equipment vendors have made PCI the de facto I/O standard for its cost-effectiveness, array of development tools, wealth of engineering resources, and a large installed base. However, current PCI-to-PCI bridges provide neither the scalability nor the high-availability required by communication platforms. The hierarchical topology of conventional PCI-to-PCI bridges increases slot count at the expense of higher latency -- an unacceptable tradeoff to communication platforms. If a conventional PCI-to-PCI bridge fails, the entire system card, I/O subsystem and/or set of line cards driven by that particular PCI-to-PCI bridge also fails, thus creating a potential entire system failure.

The PLX Adaptive Switch Fabric Architecture, therefore, was designed to eliminate the limitations of PCI ensuring that communications systems are continually operable.

In response to PLX's switch fabric architecture announcement, Ben Robitaille, president and chief executive officer of Kaparel Corp., a PLX Partner, said, "Kaparel is pleased to partner with PLX on this new adaptive switch fabric architecture project, as we see this solution as the backbone of all high-availability systems for telecommunications and data communications in the future."

"High availability and scalability to achieve increased bandwidth and sustained data rates in tens to hundreds of gigabits per second are an evolving cornerstone for improved network and storage solutions," said Paul Zorfass, senior analyst with International Data Corp/First Technology Inc. "The switch fabric architectures for implementing these solutions are the enablers for new high-performance communications and network products. The PLX technology is one of the early leaders in designing and deploying silicon solutions to implement cost-effective switch fabric interconnect parts to achieve higher-performing and improved systems throughput."

In contrast to the hierarchical architecture of PCI-to-PCI bridges, the PLX Adaptive Switch Fabric Architecture scales to hundreds of PCI slots and enables external chassis-to-chassis connections. And unlike the shared-memory architecture of PCI-to-PCI bridges, the PLX Adaptive Switch Fabric Architecture has multiple independent address domains with distinct protected address space and a built-in self-correcting mechanism to ensure high availability.

The PLX Adaptive Switch Fabric Architecture was designed specifically for edge-access communication systems which continually require bandwidth enhancements and inputs from multiple sources such as voice, data, video and wireless. As many as several hundred controllers using the architecture form a cell-based fabric of dual-counter-rotating rings, which appears to the communications system as a vast network of PCI bus segments. Each controller drives up to eight CompactPCI slots (or four PCI slots) and interoperates with other controllers as "nodes" on the ring. Each node is linked on the ring via two 16-bit wide low-voltage-differential signal links operating at 400Mz. This high-performance link connects adjacent nodes at bandwidths exceeding gigabits per second.

A unique protocol engine within each controller manages the routing of cells from the PCI source to PCI destination in a manner that is efficient and transparent to the system. The controller automatically converts PCI transactions to fabric transactions and back, and manages all error-correction or retry functions.