PCI Express verification: with the right game plan, microwave design doesn't have to be a scary proposition.

The high-tech landscape is characterized by discontinuous change. The widespread move from parallel to serial interconnect technologies is enabling device and system manufacturers to deliver radical innovations in performance, form factor, power consumption and cost.

But in order to achieve new capabilities, new products and a new era of profitable growth, we as an industry must make new technologies, like PCI Express, play. Ensuring your design's success begins in the pre-silicon environment. It is much less expensive to find and fix design problems before fabricating a hardware prototype. Moreover, doing your due diligence in pre-silicon verification can greatly reduce the amount of time it takes to bring your product to market.

Whether you are a PCB designer, a system designer or even a chip designer, pre-silicon signal integrity verification is as important as pre-silicon verification of your logic design. This is a topic that many digital designers may not he familiar with, but as PCI Express thrusts us into the world of microwave design, it will benefit us all to pay greater attention to signal integrity before we experience problems. The best way to avoid costly spins of your board or chip due to signal integrity problems is to conduct extensive signal integrity simulations before even fabricating a design prototype.

While the analog simulation is an integral step in most design processes today, it is important to consider the quality of those simulations and the validity of the information they provide. In the world of analog simulations, your simulation results are only as good as the models you use. Accurate behavioral models begin with accurate measurements of the physical interconnects in your design. Too often, we make assumptions about the behavior of our high-frequency physical interconnects based on rules of thumb and theoretical approximations. As we move higher in frequency, this becomes more dangerous. For PCI Express, with significant multigigahertz frequency content, it will pay to use measurements to build accurate models, or at least validate assumptions you are making.

TDR, TDT or Network Analyzer?

Two kinds of instruments are particularly useful in creating high-bandwidth behavioral models. Many digital designers are familiar with time domain reflectometry (TDR) and time domain transmission (TDT). The basic concept is that a very fast voltage step is launched into an interconnect or transmission line. This fast rising edge contains very high frequency content, and should be significantly faster than the edges in your design. In the case of TDR, the input is monitored for reflections indicating impedance discontinuities, and with TDT, the output is examined for distortion. In either case, this tool gives you the ability to pinpoint possible sources of signal integrity problems early in the design cycle.

Keep these considerations in mind when using TDR and TDT. First, cables, connectors and probes can cause measurement errors that are unacceptable at high frequencies by introducing impedance discontinuities into the measurement path. Some TDR/TDT instruments allow the user to normalize the measurement, filtering out the effects of errors caused by impedance discontinuities introduced by cables, test fixtures or other imperfections in your test setup. Especially if you are using your measurement results to generate models, it is extremely important that you measure your device under test, not your test setup. Second, since you will be interpreting reflections on the waveform and drawing conclusions about your design, the flatness of the TDR step generator is extremely important. Excessive overshoot and ringing on the input will lead to inaccuracies in your measurements that could either cause you to rework a design or miss flaws in your design.

For similar types of measurements, many digital design engineers today are choosing network analyzers over TDR or TDT for physical layer characterization measurements. Although they are more costly in general, network analyzers offer superior dynamic range because they employ a tuned frequency source and receiver rather than a broadband source and receiver, as with a TDR/TDT instrument. With the greater dynamic range, you are able to see smaller intricacies in your design. For a PCI Express design, the ability to measure and analyze these relatively small effects may only be necessary if your design is marginal to begin with. Using a four-port network analyzer, you will be able to make full differential measurements, and using a 16-term S-parameter matrix, you will be able to assess the quality of transmission as well as the symmetry of your design. See FIGURE 1.

[FIGURE 1 OMITTED]

PCI Express data traffic is transmitted along differential transmission lines, in part to reduce high-frequency emissions as well as the sensitivity of the transmission line to radiated energy. Symmetry is important because any asymmetry in the differential transmission line will lead to two negative effects. One is the conversion of common-mode energy to differential-mode energy, which is indicative of your design's susceptibility to radiated energy. The other effect is the conversion of differential-mode energy to common-mode energy, indicating that your design might radiate electromagnetic energy. Either of these two effects could be fatal to your design, especially since voltage swings in PCI Express can be as low as 175 mV at the receiver. Network analyzers, like TDR/TDT instruments, are also subject to errors introduced by test fixturing, and the instrument's ability to negate these effects should be factored into your interpretation of measurement results. As with the best TDR/TDT instruments, a network analyzer should allow the user to remove the effects of any impedance discontinuities introduced by test fixtures from the measurement results. This process is usually called de-embedding.

At a certain point, your confidence in your design will be high enough to move forward with a hardware prototype. Although you have performed dill gent simulations of the physical layer and logical functionality of your design, there is always a need to test in hardware. You will want to do more exhaustive verification testing than is practical to do in a simulation environment.

Keep an Eye Out

There tend to be two schools of thought regarding signal integrity verification. One approach is to only look at signal integrity if you suspect it may be the cause of a functional problem. The more conscientious approach holds signal integrity verification as a formal part of your design validation process. This second approach can greatly increase the likelihood of your design interoperating with the designs of other vendors.

The most basic way to look at a design's signal integrity is to analyze an eye diagram (FIGURE 2) by setting an oscilloscope to overlay a number of waveform trajectories to create a pattern that resembles an eye. It is useful to observe the data valid region, or eye opening. This type of analysis on PCI Express presents two particular challenges. First, the clock is embedded in the data using an 8b/10b encoding scheme. This means that there is no discrete clock signal to use as a trigger for the oscilloscope, and that some method of clock recovery must be employed. The second challenge is that PCI Express provides the designer the option of employing a spread spectrum clock. This is done to spread the frequency content contained within the data stream over a wider spectrum to eliminate a large magnitude of radiated energy at any one frequency. But in order for your measurement to be relevant, the clock recovery method used for the measurement must closely match the clock recovery in the design. In other words, the low-frequency phase modulation from the spread spectrum clock must be rejected so the data is analyzed the way the receiver will see it.

[FIGURE 2 OMITTED]

Another very important consideration with regard to signal integrity measurements on PCI Express is the high-frequency content contained in the data stream. Due to the data rate and very fast slew rates employed in PCI Express (rise and fall times at the transmitter can be as low as 50 psec), any relevant measurement must be made with an instrument with adequate bandwidth. Typically, signal integrity measurements will be made with an oscilloscope--either a real-time digitizing oscilloscope or an equivalent time-sampling oscilloscope. Equivalent time-sampling oscilloscopes tend to be much higher in bandwidth, and sub-sample the signal under test over a large number of cycles to reconstruct the waveform. A real-time oscilloscope, on the other hand, samples the signal under test at a much higher rate, ideally greater than the Nyquist frequency relative to the highest significant frequency content being measured. At this writing, PCI Express is pushing real-time oscilloscope technology to its limits. However, since many of the measurements mandated by the PCI Express specification must be made in real time, it is imperative that measurements be made with care.

Since many design teams will not have the luxury of building a connectorized test board especially for signal integrity validation, oscilloscope probing also becomes a major concern. State-of-the-art for real-time oscilloscopes is currently 6 GHz bandwidth and 20 Gigasamples per second per channel sample rate. Since this level of performance is barely adequate for PCI Express, it is imperative that any probing solution you use not further limit the bandwidth of your measurement. In order to make certain that you are taking advantage of the full bandwidth of your oscilloscope, you should use probes that have at least 7 GHz of bandwidth. And due to the differential topology of PCI Express, good measurements should be made with differential probes.

It is wise to look beyond banner specifications. Not only are specifications like bandwidth and sample rate critical if you are going to make accurate and relevant measurements, but it is also important to consider issues such as the flatness of the instrument's transfer function and the electrical loading a probe will introduce to the circuit under test.

Real-time oscilloscopes are no longer designed to have a Gaussian frequency response because such a design leads to some aliasing of out-of-band frequency components of a signal under test. Rather, real-time oscilloscopes today are being designed with "maximally flat" frequency response. Ideally, your instrument's transfer function would be perfectly flat out to its specified bandwidth and fall off like a "brick wall" filter.

In practice, however, there will be deviations from the ideal. High-frequency peaking, or amplifying higher frequency content at a higher ratio than lower frequency content, is a common pitfall when designing a maximally flat filter and will lead to inaccuracies in the waveform your instrument shows you. Make sure you analyze a true transmitted response curve (Vin/Vout) of any instrument you are considering for high-bandwidth measurements to determine to what degree your measurements will reflect reality.

It is also wise to analyze a high-bandwidth behavioral load model of any probe you are considering using to determine how it will affect the behavior of your circuit when making measurements. All probes will introduce some electrical load to your system, but clearly this effect should be minimized. It is wise to plug these models into your pre-silicon simulations in order to analyze how significant the effect will be. All models should be based on measurements taken in the physical world, preferably with a high-frequency network analyzer.

For some of you, PCI Express will mark your transition into the world of microwave design. Knowledge of fundamentals such as transmission line theory and frequency domain analysis will be critical to the success of your efforts to bring a PCI Express product to market. Signal integrity considerations are a small but important part of your design verification process. DFT should never be an afterthought, but rather an integral part of your design verification strategy.

RANDY WEBER is an account manager at Agilent Technologies. He has a BSEE from Santa Clara University, and has been at Agilent for five years. Weber can be reached at randy [e-mail].