PCI Express: connectivity for the next generation.

Since its inception in 1992, the PCI bus has become the I/O backbone of nearly every computing platform, and is the primary interface for desktop computers and peripheral cards. PCI technology has played a large part in the standardization of computer hardware, and has provided an evolving platform for increasing performance demands.

The PCI bus was designed for high-speed, efficient data movement using the local bus architecture--directly interfacing with the computer's central processing unit (CPU). Performance of the PCI bus has been continually improved to keep pace with increased bandwidth requirements by increasing clock speeds and widening buses. However, those methods have begun to run up against some boundaries. Increasing bus speed is no longer practical, due to the effects of increased signal skew. Widening the bus complicates board and silicon layout. Close examination of PCI signaling technology reveals that the parallel bus architecture of PCI is reaching its performance limits.

To combat these performance limitations, the PCI Express architecture was recently introduced to provide a scalable, high-speed, serial I/O bus. While the new bus maintains backward compatibility with existing PCI applications and drivers, lessening the burden on developers, the form factor of the new PCI Express slots differs from the current PCI slots, meaning any end user wishing to utilize a PCI Express card must have a computer equipped to handle the new standard.

PCI Development

Increasing bandwidth and performance requirements have required the continuing evolution of the PCI architecture. The original PCI bus was designed to support 2D graphics, higher-performance disk drives and local network. Not long after its introduction, though, the bandwidth of 3D graphics subsystems outstripped available bandwidth. In order to deal with the increasing demands on the PCI bus, the platform architecture has evolved by offloading various functions to higher-bandwidth PCI derivatives, including AGP and PCI-X. This helped free up much needed bandwidth for communications and I/O operations.

While offloading some functions did help increase the performance of the PCI standard, it became evident that the performance ceiling of the bus was quickly being approached. That fact, combined with the arrival of technologies such as 8-Gb and 10-Gb Fibre Channel, along with 10-Gb Ethernet, helped clearly define the need for a new, faster I/O bus.

Why choose PCI Express?

Although sufficient to support existing technology such as Fibre Channel, Ethernet and SCSI storage, the PCI architecture falls short in supporting planned technologies such as 8-Gigabit and 10-Gb Fibre Channel as well as 10-Gigabit Ethernet. Trying to use traditional parallel PCI to support these advanced networking technologies would effectively saturate all available bandwidth. The existing PCI architecture is also ill-equipped to deal with innovations such as RAID arrays, higher CPU speeds, and faster memories.

Those are not the only issues concerning PCI. Over the past decade, video performance requirements have doubled almost every two years, while High Definition (HD) video and its high bandwidth requirements are becoming more prevalent.

Additionally, there are a growing number of real-time applications, such as video-on-demand and audio redistribution that require faster bus architectures. Today's software applications are more demanding of platform hardware, particularly the I/O subsystems. Streaming data from various video and audio sources are now commonplace on desktop machines, and there is no baseline support for this time dependent data within PCI or PCI-X specifications. Finally, many communications applications and embedded PC control systems also process data in real time.

Serial Technology: PCI Express

As the demands on PCI have increased, the limitations inherent in bus architecture are creating an overall system bottleneck. Options such as increasing bus speed and widening the bus are simply not practical. As a result, serial interconnects that reduce pin count, simplify board layouts and offer speed, scalability, reliability and flexibility not possible with parallel buses are needed.

In order to meet these ever-changing performance requirements, the PCI Express standard was developed. PCI Express is a low-cost, highly scalable, serial I/O interconnect that retains full software compatibility with the existing PCI standard. PCI Express will serve as a general purpose I/O interconnect for a wide variety of future computing and communications platforms. Key PCI attributes, such as its usage model and software interfaces are maintained, while the less desirable aspects of PCI, such as its bandwidth limitations and parallel bus implementation, are replaced by a fully serial interface. Fewer common interconnects also reduce complexity in software and hardware, and all information (data as well as management information) is transmitted in-band, which reduces costs and simplifies the overall architecture.

With data transfer rates of 2.5 Gb/second per lane, per direction, PCI Express easily scales beyond the existing PCI architecture. Because the link is bidirectional, the effective raw data transfer rate is 5 Gb/second. The bandwidth of a PCI Express link can be scaled by adding signal pairs to form multiple lanes between two devices. The specification supports x1, x4, x8, x12, x16 and x32 lane widths and stripes the data across links accordingly.

The new serial bus technology is expected to allow PCI Express transmission rates to keep pace with processor and I/O advances through the next decade, if not longer. PCI Express offers a point-to-point link dedicated to each device, as opposed to the PCI shared bus, meaning devices do not have to share bandwidth. There are opportunities for lower latency (or delay) in server architectures. In contrast to PCI, PCI Express has minimal sideband signals and the clocks and addressing information are embedded in the data. Finally, because PCI Express is a serial technology, the bandwidth per I/O connector pin is much higher when compared to PCI.

Advanced features inherent in the PCI Express standard include Quality of Service (QoS) via isochronous channels for guaranteed bandwidth delivery when required, advanced power management, support for real-time data traffic, data integrity and error handling, and native hot plug/hot swap support.

The Transition

PCI Express will eventually replace PCI, PCI-X and AGP parallel buses. Systems requiring the additional performance and features provided by PCI Express, such as those requiring high-end graphics performance, were among the first to migrate. NVIDIA and ATI Technologies have already announced that all new graphics cards from both companies will utilize PCI Express. Other examples of devices immediately benefiting from PCI Express on client machines include those which utilize the 1394 standard, Gigabit Ethernet, and TV tuner cards.

Another segment quick to adopt PCI Express was the desktop and server marketplace. Both Intel and AMD have released chipsets which support PCI Express. Systems integrators in this segment have found that PCI Express' bandwidth and pin count has benefited them greatly, while OEMs have taken advantage of protocol bridges to utilize their legacy designs into the PCI Express architecture, shortening development time.

Client system boards and workstations are migrating from PCI to x1 PCI Express connectors, while workstations which utilize PCI-X are moving to x4 PCI Express connectors. The current AGP bus is being replaced with an x16 PCI Express connector.

PCI-X will co-exist with, and will eventually be replaced by x4 and x8 PCI Express connectors in server systems. Those systems will likely use PCI Express for Ultra320 SCSI cards, Fibre Channel Host Adapters, and Gigabit Ethernet cards.

Thanks to full software compatibility with the existing PCI standard, and the layered architecture of PCI Express that supports existing PCI applications and drivers, the transition from PCI to PCI Express has been, and should continue to be a smooth one.

Industry support has been strong thus far, another factor in the relative ease of the transition. Both Intel and AMD, as noted earlier, have released several chip sets which natively support the PCI Express standard. These chip sets are becoming the backbone of new mainstream PCs currently being released.

Many other vendors, including ATTO Technology, Inc., are currently developing PCI Express products, such as host adapters. These development efforts are made simpler and faster by PCI Express' backward compatibility with PCI applications and drivers. These products are being combined with the latest I/O and storage technologies to provide unique, advanced capabilities to support a wide range of emerging and maturing markets.

The PCI Express architecture offers many advantages over the existing PCI standard. Features such as higher bandwidth and low pin counts, along with advanced capabilities such as hot plug/hot swap, make PCI Express an attractive new option for end users and manufacturers alike. Since the PCI Express architecture allows for a relatively easy transition from PCI, and because it provides many performance advantages over PCI, it is expected that the move from PCI to PCI Express will be a relatively painless one.

ATTO Technology is located in Amherst, New York.

www.attotech.com