PCB stackup analysis and design, Part 2: Stackup analysis can help to optimize layer count, trace width and spacing and electrical performance.PCB PCB: see polychlorinated biphenyl.
in full polychlorinated biphenyl
Any of a class of highly stable organic compounds prepared by the reaction of chlorine with biphenyl, a two-ring compound. stackup stack·up
A deployment of aircraft circling an airport at designated altitudes while awaiting instructions to land. , it is essential to consider crosstalk (1) requirements. Depicted by FIGURE 4 are two single-ended traces having line width W, thickness t, edge-to-edge separation Sn and height over reference plane H. Er is the relative dielectric constant dielectric constant
See permittivity. of the substrate.
In order to minimize crosstalk, it is desirable to set H as small and Sn as large as allowed by board target
impedance and routing restrictions. (14) The effect of these stackup parameters on crosstalk (15) is disclosed by Equation 1 (FIGURE 5).
[L.sub.m] is mutual inductance mutual inductance
n. Abbr. M
The ratio of the electromotive force in a circuit to the corresponding change of current in a neighboring circuit. between two neighboring wires, H equals the thickness of the dielectric substrate and L is the line inductance. The center-to-center spacing (s) and edge-to-edge spacing ([S.sub.n]) for two traces of width W are directly related as shown by Equation 2 (Figure 5).
Crosstalk requirements control trace separation (pitch), which in turn influences board density and the number of routing layers. From Equations 1 and 2, it follows that crosstalk noise (between two neighboring traces) being proportional to mutual inductance, decreases as Sn increases or H decreases. Optimizing trace separation is also valuable for controlling crosstalk between two coupled differential pairs, as illustrated in FIGURE 6.
Crosstalk between differential pairs 1 and 2 can be diminished by widening Sn. A study of far-end crosstalk (FEXT (Far End Cross(X) Talk) A measurement of crosstalk between two wire pairs taken at the far end of the line. See ELFEXT and NEXT. ) and crosstalk-induced jitter A flicker or fluctuation in a transmission signal or display image. The term is used in several ways, but it always refers to some offset of time and space from the norm. For example, in a network transmission, jitter would be a bit arriving either ahead or behind a standard clock cycle involving two edge-coupled differential pairs of W = 5 mil and interapair separation Sp = 5 mil, revealed that increasing the pair-to-pair spacing Sn from 5 mils to 20 mils can significantly reduce FEXT (16) and deterministic jitter Deterministic jitter (or DJ) is a type of jitter with a known non-Gaussian probability distribution. The other major class of jitter is non-deterministic, or random jitter. (D J). Other measures to avoid crosstalk problems include minimizing parallel run lengths, incorporating guard traces (15) and orthogonally routing the signal lines which belong to adjacent routing layers.
[FIGURE 4 OMITTED]
To attain good signal integrity, a clean (15) unobstructed return path is demanded for high-speed signals. Signal and power quality degradation can occur in PCBs and IC packages due to high-speed traces traversing (17) plane-splits.
Plane layers fulfill several duties in power distribution networks (PDNs). They can transfer DC current from source to load, connect bypass capacitors to active components and furnish a return path (18) for the signals. Current flows on power distribution in a manner to diminish total impedance. (19) At low frequencies, this translates to minimizing resistance by spreading (20) over every possible path. At high frequencies, the return current crowds under the signal (on reference plane) to minimize inductance.
It is important to avoid splits on ground or power planes, but there are situations when it is inevitable. (20) For instance, power islands and moats arise when multiple powers are incorporated on the same plane. Sometimes, it is necessary to allow a plane layer cut-out beneath a connector (21) in order to lessen the mounting pad capacitance.
Under such circumstances, when cutouts on reference planes are unavoidable, it is critical not to route high-speed buses over such voids (unless the plane with slots is sandwiched between two uniform/continuous planes).
The return current path is also interrupted whenever a signal transitions from one layer to another and changes reference planes. It is then desirable to place near the signal via (22) another via (if both reference planes are of same type) or a decoupling capacitor A decoupling capacitor is a capacitor used to decouple one part of an electrical network (circuit) from another. Noise caused by other circuit elements is shunted through the capacitor reducing the effect they have on the rest of the circuit. (if one reference plane is a ground while the other one is power). This can furnish for the return current a high-frequency lane between the two reference planes.
[FIGURE 5 OMITTED]
[FIGURE 6 OMITTED]
Thickness of metal (i.e. plane and signal) layers is a significant option when constructing PCB stackup. Thicker cladding offers lower resistance and symbolizes a good selection for power planes (19). Thinner cladding sustains narrow lines with superior width control; hence, thin cladding is often a logical preference for signal layers to achieve high density routing.
Utilizing 0.5 oz copper for signal layers is a good choice for impedance control (3) since only a very small amount of etching is necessary to produce a trace. This allows controlling the trace width to within 0.5 mils. However, there are also cases in which thicker traces are desired in order to decrease the trace's DC resistance (or for realizing superior thermal performance), although it is more difficult to attain impedance control for thicker traces.
Accomplishing impedance control for high-speed, single-ended signals (such as memory buses and CPU CPU
in full central processing unit
Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. interfaces) and differential pairs (high-speed serial-links, differential clocks, etc.) is vital in stackup design.
Mathematical equations exist for calculating single-ended and differential impedance (23). These formulas offer useful insight regarding how impedance depends on various stackup parameters (e.g., dielectric constant, trace width, dielectric thickness). For instance, Equation 3 (Figure 5) which is an IPC (1) (InterProcess Communication) The exchange of data between one program and another either within the same computer or over a network. It implies a protocol that guarantees a response to a request. recommended (23) approximation for microstrip impedance, reveals that Zo decreases as the dielectric constant (Er) increases, copper thickness (t) increases or trace width (W) increases. Furthermore, Zo increases as dielectric height H increases. Equation 4 (Figure 5), which applies to edge-coupled microstrip using FR4 material (23), illustrates that differential impedance Zdiff is a function of Zo (the uncoupled single-ended characteristic impedance This article is about impedance in electronics. For characteristic acoustic impedance, see acoustic impedance.
The characteristic impedance or surge impedance of a uniform transmission line, usually written for each trace), edge-to-edge separation between traces Sn and dielectric thickness H.
Impedance formulas can provide helpful insight and more precise results than rules of thumb approximations, but the accuracy of such analytical techniques is usually limited to about 10%. Ascertaining impedance to a higher degree of exactness would require the use of a field solver program.
Whenever a PCB undergoes modifications, it is necessary to perform stackup analysis (24). Such assessment considers optimum number of layers, board size, routing density, copper weight, power needs, PCB thickness, dielectric materials Dielectric materials
Materials which are electrical insulators or in which an electric field can be sustained with a minimal dissipation of power. Dielectrics are employed as insulation for wires, cables, and electrical equipment, as polarizable media for , trace widths/separation, most favorable impedance, price and manufacturability.
Application of HyperLynx Stackup Editor for impedance planning is illustrated by FIGURES 7. The Stackup Editor allows adding or subtracting layers and incorporating soldermask.
For each dielectric, it permits selecting technology (prepreg or core), thickness, dielectric constant and loss tangent. For metal layers, it allows defining metal type (for correct resistivity resistivity
Electrical resistance of a conductor of unit cross-sectional area and unit length. The resistivity of a conductor depends on its composition and its temperature. and temperature coefficient The temperature coefficient is the relative change of a physical property when the temperature is changed by 1 K.
In the following formula, let R be the physical property to be measured, let T be the temperature of at which the property is measured. ). Trace widths and thickness can be specified for each signal layer. The Zo Planning tab allows for specifying target impedance (for single-ended or differential pairs) and then solving for various parameters (trace width, separation).
[FIGURE 7 OMITTED]
Figure 7 shows a stackup consisting of eight layers. An eight-layer stack (5) can satisfy several desirable requirements, including multiple ground and power layers. In this case each signal layer is adjacent to a tightly coupled See tight coupling. plane layer, and the signal layers are located between planes layers (and are thereby being well shielded).
In order to minimize warping, it is desirable for the stackup to be symmetrical and well balanced (25). Normally, an N-layer PCB includes N metal layers separated by N-1 dielectrics, and N should be an even number to avoid warpage (19).
Another measure to accomplish uniformity is to add dummy copper pads (thieving) to open areas on the PCB's outer layers. This aids in attaining a uniform copper distribution across the whole board surface. PCD&F
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ABE Association of Building Engineers (ABBAS) RIAZI is a senior staff scientist - hardware development with Broadcom Corporation in Irvine, California Irvine is an incorporated city in Orange County, California, United States. It is a planned city, mainly developed by the Irvine Company since the 1960s. Formally incorporated on December 28 1971, the 69.7 square mile (180.5 km²) city has a population of 202,079 (as of 2007). and can be reached at firstname.lastname@example.org.
I am grateful to Messrs. Nanoo (Frederik) Staal, Mohammad Tabatabai, Afshin Momtaz, Matthew Isaacs and Neven Pischl of Broadcom Corporation, and Ms. Debi Sorensen of Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. Corporation.
(14.) Stephen H. Hall, Garrett W. Hall and James A. McCall, "High-Speed Digital System Design, A Handbook of Interconnect Theory and Design Practices," John Wiley John Wiley may refer to:
- John Wiley & Sons, publishing company
- John C. Wiley, American ambassador
- John D. Wiley, Chancellor of the University of Wisconsin-Madison
- John M. Wiley (1846–1912), U.S.
(15.) Ernie Buterbaugh, "Perfect Timing A design Guide for Clock Generation and Distribution;' Cypress Semiconductor Corporation, 2002, Chapter 6.
(16.) Greg Edlund, "Timing Analysis and Simulation for Signal Integrity Engineers," Prentice Hall, 2007, pgs. 196-197.
(17.) Abe Riazi, "Effects of Plane Splits on High-Speed Signals, Part 2" Printed Circuit Design & Manufacture, April 2007, pgs. 16-17.
(18.) Istvan Novak and Jason R. Miller, "Frequency-Domain Characterization of Power Distribution Networks" Artech House inc., 2007, p. 67.
(19.) Brian Young, "Digital Signal Integrity Modeling and Simulation with Interconnects and Packages" Prentice Hall PTR PTR Pointer (as used in DNS records; an address points to a name)
PTR Proton Transfer Reaction
PTR Pupil/Teacher Ratio
PTR Public Test Realm (gaming, World of Warcraft) , 2001, pgs. 410-413.
(20.) Abe Riazi, "Effects of Plane Splits on High-Speed Signals, Part 1" Printed Circuit Design & Manufacture, February 2007, pgs. 16-17.
(21.) "Virtex-4 Power System Performance;' Xilinx Signal Integrity Seminar Series, March 28, 2006.
(22.) Henry W. Ott, "PCB Stack-Up Part 6" Henry Ott Consultants, 2002.
(23.) Eric Bogatin, "Signal Integrity Simplified," Prentice Hall PTR, 2004, p. 260, pgs. 489-490.
(24.) Chuck Troia. "Stackup Analysis Using HyperLynx" IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. SCV SCV Santa Clarita Valley (California)
SCV Sons of Confederate Veterans
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SCV Singapore Cable Vision
SCV Special Category Visa (Australia)
SCV StarHub Cable Vision Chapter of the EMC (1) (EMC Corporation, Hopkinton, MA, www.emc.com) The leading supplier of storage products for midrange computers and mainframes. Founded in 1979 by Richard J. Egan and Roger Marino, EMC has developed advanced storage and retrieval technologies for the world's largest companies. Society, January 10, 2006.
(25.) Patrick Carrier, "Proactive High-Speed PCB Stackup Planning" Mentor Graphics Webinar, 2004.
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|Title Annotation:||INTERCONNECT STRATEGIES|
|Author:||Riazi, Abe "Abbas"|
|Publication:||Printed Circuit Design & Fab|
|Date:||Dec 1, 2008|
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