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PCB stackup analysis and design, Part 2: Stackup analysis can help to optimize layer count, trace width and spacing and electrical performance.

WHEN DESIGNING a PCB stackup, it is essential to consider crosstalk (1) requirements. Depicted by FIGURE 4 are two single-ended traces having line width W, thickness t, edge-to-edge separation Sn and height over reference plane H. Er is the relative dielectric constant of the substrate.

In order to minimize crosstalk, it is desirable to set H as small and Sn as large as allowed by board target

impedance and routing restrictions. (14) The effect of these stackup parameters on crosstalk (15) is disclosed by Equation 1 (FIGURE 5).

[L.sub.m] is mutual inductance between two neighboring wires, H equals the thickness of the dielectric substrate and L is the line inductance. The center-to-center spacing (s) and edge-to-edge spacing ([S.sub.n]) for two traces of width W are directly related as shown by Equation 2 (Figure 5).

Crosstalk requirements control trace separation (pitch), which in turn influences board density and the number of routing layers. From Equations 1 and 2, it follows that crosstalk noise (between two neighboring traces) being proportional to mutual inductance, decreases as Sn increases or H decreases. Optimizing trace separation is also valuable for controlling crosstalk between two coupled differential pairs, as illustrated in FIGURE 6.

Crosstalk between differential pairs 1 and 2 can be diminished by widening Sn. A study of far-end crosstalk (FEXT) and crosstalk-induced jitter involving two edge-coupled differential pairs of W = 5 mil and interapair separation Sp = 5 mil, revealed that increasing the pair-to-pair spacing Sn from 5 mils to 20 mils can significantly reduce FEXT (16) and deterministic jitter (D J). Other measures to avoid crosstalk problems include minimizing parallel run lengths, incorporating guard traces (15) and orthogonally routing the signal lines which belong to adjacent routing layers.


To attain good signal integrity, a clean (15) unobstructed return path is demanded for high-speed signals. Signal and power quality degradation can occur in PCBs and IC packages due to high-speed traces traversing (17) plane-splits.

Plane layers fulfill several duties in power distribution networks (PDNs). They can transfer DC current from source to load, connect bypass capacitors to active components and furnish a return path (18) for the signals. Current flows on power distribution in a manner to diminish total impedance. (19) At low frequencies, this translates to minimizing resistance by spreading (20) over every possible path. At high frequencies, the return current crowds under the signal (on reference plane) to minimize inductance.

It is important to avoid splits on ground or power planes, but there are situations when it is inevitable. (20) For instance, power islands and moats arise when multiple powers are incorporated on the same plane. Sometimes, it is necessary to allow a plane layer cut-out beneath a connector (21) in order to lessen the mounting pad capacitance.

Under such circumstances, when cutouts on reference planes are unavoidable, it is critical not to route high-speed buses over such voids (unless the plane with slots is sandwiched between two uniform/continuous planes).

The return current path is also interrupted whenever a signal transitions from one layer to another and changes reference planes. It is then desirable to place near the signal via (22) another via (if both reference planes are of same type) or a decoupling capacitor (if one reference plane is a ground while the other one is power). This can furnish for the return current a high-frequency lane between the two reference planes.



Thickness of metal (i.e. plane and signal) layers is a significant option when constructing PCB stackup. Thicker cladding offers lower resistance and symbolizes a good selection for power planes (19). Thinner cladding sustains narrow lines with superior width control; hence, thin cladding is often a logical preference for signal layers to achieve high density routing.

Utilizing 0.5 oz copper for signal layers is a good choice for impedance control (3) since only a very small amount of etching is necessary to produce a trace. This allows controlling the trace width to within 0.5 mils. However, there are also cases in which thicker traces are desired in order to decrease the trace's DC resistance (or for realizing superior thermal performance), although it is more difficult to attain impedance control for thicker traces.

Accomplishing impedance control for high-speed, single-ended signals (such as memory buses and CPU interfaces) and differential pairs (high-speed serial-links, differential clocks, etc.) is vital in stackup design.

Mathematical equations exist for calculating single-ended and differential impedance (23). These formulas offer useful insight regarding how impedance depends on various stackup parameters (e.g., dielectric constant, trace width, dielectric thickness). For instance, Equation 3 (Figure 5) which is an IPC recommended (23) approximation for microstrip impedance, reveals that Zo decreases as the dielectric constant (Er) increases, copper thickness (t) increases or trace width (W) increases. Furthermore, Zo increases as dielectric height H increases. Equation 4 (Figure 5), which applies to edge-coupled microstrip using FR4 material (23), illustrates that differential impedance Zdiff is a function of Zo (the uncoupled single-ended characteristic impedance for each trace), edge-to-edge separation between traces Sn and dielectric thickness H.

Impedance formulas can provide helpful insight and more precise results than rules of thumb approximations, but the accuracy of such analytical techniques is usually limited to about 10%. Ascertaining impedance to a higher degree of exactness would require the use of a field solver program.

Whenever a PCB undergoes modifications, it is necessary to perform stackup analysis (24). Such assessment considers optimum number of layers, board size, routing density, copper weight, power needs, PCB thickness, dielectric materials, trace widths/separation, most favorable impedance, price and manufacturability.

Application of HyperLynx Stackup Editor for impedance planning is illustrated by FIGURES 7. The Stackup Editor allows adding or subtracting layers and incorporating soldermask.

For each dielectric, it permits selecting technology (prepreg or core), thickness, dielectric constant and loss tangent. For metal layers, it allows defining metal type (for correct resistivity and temperature coefficient). Trace widths and thickness can be specified for each signal layer. The Zo Planning tab allows for specifying target impedance (for single-ended or differential pairs) and then solving for various parameters (trace width, separation).


Figure 7 shows a stackup consisting of eight layers. An eight-layer stack (5) can satisfy several desirable requirements, including multiple ground and power layers. In this case each signal layer is adjacent to a tightly coupled plane layer, and the signal layers are located between planes layers (and are thereby being well shielded).

In order to minimize warping, it is desirable for the stackup to be symmetrical and well balanced (25). Normally, an N-layer PCB includes N metal layers separated by N-1 dielectrics, and N should be an even number to avoid warpage (19).

Another measure to accomplish uniformity is to add dummy copper pads (thieving) to open areas on the PCB's outer layers. This aids in attaining a uniform copper distribution across the whole board surface. PCD&F

DR. ABE (ABBAS) RIAZI is a senior staff scientist - hardware development with Broadcom Corporation in Irvine, California and can be reached at


I am grateful to Messrs. Nanoo (Frederik) Staal, Mohammad Tabatabai, Afshin Momtaz, Matthew Isaacs and Neven Pischl of Broadcom Corporation, and Ms. Debi Sorensen of Mentor Graphics Corporation.


(14.) Stephen H. Hall, Garrett W. Hall and James A. McCall, "High-Speed Digital System Design, A Handbook of Interconnect Theory and Design Practices," John Wiley and Sons, Inc., 2000, p. 68, pgs. 82-90, p. 115.

(15.) Ernie Buterbaugh, "Perfect Timing A design Guide for Clock Generation and Distribution;' Cypress Semiconductor Corporation, 2002, Chapter 6.

(16.) Greg Edlund, "Timing Analysis and Simulation for Signal Integrity Engineers," Prentice Hall, 2007, pgs. 196-197.

(17.) Abe Riazi, "Effects of Plane Splits on High-Speed Signals, Part 2" Printed Circuit Design & Manufacture, April 2007, pgs. 16-17.

(18.) Istvan Novak and Jason R. Miller, "Frequency-Domain Characterization of Power Distribution Networks" Artech House inc., 2007, p. 67.

(19.) Brian Young, "Digital Signal Integrity Modeling and Simulation with Interconnects and Packages" Prentice Hall PTR, 2001, pgs. 410-413.

(20.) Abe Riazi, "Effects of Plane Splits on High-Speed Signals, Part 1" Printed Circuit Design & Manufacture, February 2007, pgs. 16-17.

(21.) "Virtex-4 Power System Performance;' Xilinx Signal Integrity Seminar Series, March 28, 2006.

(22.) Henry W. Ott, "PCB Stack-Up Part 6" Henry Ott Consultants, 2002.

(23.) Eric Bogatin, "Signal Integrity Simplified," Prentice Hall PTR, 2004, p. 260, pgs. 489-490.

(24.) Chuck Troia. "Stackup Analysis Using HyperLynx" IEEE SCV Chapter of the EMC Society, January 10, 2006.

(25.) Patrick Carrier, "Proactive High-Speed PCB Stackup Planning" Mentor Graphics Webinar, 2004.
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Author:Riazi, Abe "Abbas"
Publication:Printed Circuit Design & Fab
Date:Dec 1, 2008
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