PCB database viewing for SI analyses, Part 2: signal integrity modeling, simulation and measurements can demand frequent examination of the PCB database.

HIGH-SPEED DIFFERENTIAL pairs, traces traversing reference plane splits, BGA escape regions and relative routing of adjacent signal layers are frequently inspected for SI objectives. Differential nets are often closely examined due to their prevalence and significance in high-speed PCBs. For instance, they are evaluated for length matching (7), and other factors that can cause skew (9). When a differential pair includes termination resistors, DC blocking capacitors, via pairs or serpentine sections, it needs to be checked that such elements are implemented symmetrically (10,11).

Sometimes a PCB design needs to be inspected for high-speed traces crossing slots (12) in a neighboring power/ ground plane. An example is illustrated by FIGURE 5. It displays several traces close to and routed over splits in the reference planes. This may cause impedance discontinuities, crosstalk and other undesirable effects (12). Figure 5 also shows stitching capacitors aimed at reducing the adverse effects associated with high-speed traces crossing plane cutouts. This PCB database was evaluated using the Allegro Free Physical Viewer, by turning on the desired signal layer and its reference plane with other layers turned off.

[FIGURE 5 OMITTED]

[FIGURE 6 OMITTED]

The Allegro viewer can be utilized to open board files having .brd extensions. Its menu and toolbar are depicted by FIGURE 6. It contains file Open, several zoom features (such as Zoom Points, Fit, In, Out, Previous), Color (and visibility), Show Element, Measure, Hilight, De-hilight, Grid Toggle, Rats Toggle, and Help.

One application of the Show Element feature is to ascertain trace lengths, as illustrated by FIGURE 7.

The Show Element window (Figure 7) displays the total etch length, the percent and the total Manhattan lengths. The Manhattan length defines the shortest path (13) between two ends of the connection if routed orthogonally. In addition to net length, the Show Element window can reveal other information such as trace widths and properties/electrical constraints associated with the net.

It needs to be noted, when viewing nets with series components such as a resistor or a capacitor, that the trace can have sections of different net names. For instance, a clock line with a driver U1, a series resistor R1 and a receiver U2, may have a short section (from pin of U1 to one pin of R1) with net name CLK and a long section (from the other pin of R1 to pin of U2) named CLKR. The CLK and CLKR segment lengths then need to be added for calculating the total trace length. When inspecting such multiple sectioned nets, it can also prove beneficial to review the schematic drawing of the design to gain a more clear understanding of components and topology.

[FIGURE 7 OMITTED]

The wildcard character (*) of Allegro Viewer can be utilized for various applications. For instance, it is possible to simultaneously examine a family of nets and to ascertain the min/max routed lengths for a group of traces belonging to a bus. The zoom and pan features of this software can be applied to closely inspect various PCB features including long nets.

As mentioned in Part 1, the examples in this column utilize Cadence Allegro; however, similar inspections and SI evaluations are feasible on databases produced by other PCB design programs.

Several features of BGA breakout as depicted by FIGURE 8 deserve appraisal. Connections between differential pairs and BGA balls, the necking down of traces, which can cause impedance discontinuities, and power delivery to the chip usually demand inspection.

It is desirable that traces routed between neighboring pins (or vias) be properly centered and to avoid routing over plane splits (and other plane voids such as anti-pads) whenever feasible.

BGA escape regions often routed in a radial (14) fashion (out from the center of the land array) can produce a horizontal and a vertical slot useful for placing surface-mount decoupling capacitors on the bottom layer. It also allows superior power feed (wider power channel) to the BGA.

[FIGURE 8 OMITTED]

[FIGURE 9 OMITTED]

It is often necessary to identify test or access points for oscilloscope probing and signal measurements. Some standard (1) SI measurements include: rise/fall times, propagation delay, noise margin, timing budget, overshoot/undershoot, and crosstalk. A suitable access point for probing is often on the bottom layer underneath the BGA at a dog-bone via. A ground close to the signal pin is also needed for probing to minimize ground loops and associated inductive noise when applying oscilloscope probes (15).

When the PCB stackup includes two adjacent signal layers such as dual (or broad-side-coupled) stripline structure as shown in FIGURE 9, it is sometimes necessary to evaluate the routing.

FIGURE 10 displays numerous nets belonging to two such adjacent inner layers. In certain regions, the traces of the two layers are routed parallel, and in other areas, they are orthogonal to each other.

For high-speed PCBs, it is preferable that signals on adjacent layers (16,17) be routed in an orthogonal (90 degree conductor crossing) fashion to minimize crosstalk. However, coupling would also depend on such factors as separation distance between the layers, the parallelism length, driver strength and signal edge rates. It is preferable (for diminishing crosstalk) to place the signal layers close to the reference planes, to use thin trace widths, short parallel lengths and offset the traces. The exact magnitude of crosstalk can be ascertained via modeling and simulation.

An outstanding resource for exploring additional information related to topics discussed in this column is the Signal Integrity List email reflector (SI-LIST). It is free to subscribe to the SI-LIST and the list archives are available (18) for viewing.

[FIGURE 10 OMITTED]

ACKNOWLEDGEMENTS

My gratitude to Greg Albers, Peter Arnold, Mark Furnace, and Suresh Vegesna for reviewing the manuscript and furnishing excellent feedback.

REFERENCES

(9.) Bruce Archambeault, "EMI/EMC Concerns for High-Speed Differential Signals," Printed Circuit Design & Manufacture, July 2007, PR 16-17.

(10.) Abe Riazi, " Differential Signal routing Requirements" Printed Circuit Design & Manufacture, February 2004, PP. 22-23.

(11.) Abe Riazi, " Avoiding Differential Pair Routing Violations," Printed Circuit Design & Manufacture, August 2004, PP. 26-29.

(12.) Abe Riazi, "Effects of Plane Splits on High-Speed Signals, Part 1" Printed Circuit Design & Manufacture, February 2007, PP. 16-17.

(13.) Lee W. Ritchey, Right the First Time: A Practical Handbook On High-Speed PCB And System Design, Vol. 1, Speeding Edge, 2003, PP. 222-223.

(14.) Bernard Voss, "BGA Power Delivery Routing" Printed Circuit Design, September 2002, P. 33.

(15.) Peter D. Hiscocks, James Gatson, "Oscilloscope Probes: Theory and Practice" Syscomp Electronic Design Limited, July 12, 2007.

(16.) Leonard Dieguez and Salman Jiva, "Altera Gigabit Channel Design Guidelines," Signal Integrity Net Seminar Series, 2007.

(17.) Bernard Voss, "Tricks of High-Speed P.CB Stack-Up" Printed Circuit Design, April 2002, P. 18.

(18.) SI-LIST archives are viewable at freelists. org/archives/si-list. Old (prior to June 6, 2001) archives available at qsl.net/wb6tpu.

Ed.: Part 1 appeared in the August issue. Both parts are available online at pcdandm.com/cms/content/ view/3700/95/

DR. ABE (ABBAS) RIAZI is a senior staff electronic design scientist with ServerWorks (a Broadcom Company) in Santa Clara, CA. He can be reached at ariazi@ serverworks.com.