Printer Friendly
The Free Library
5,665,456 articles and books
Member login
User name  
Password 
 
Join us Forgot password?

P.A. Semi Successfully Develops 65nm, 2.5 GHz PLLs For PWRficient(TM) Processor Using Berkeley Design Automation's Noise Analyzer.


SANTA CLARA Santa Clara, city, Cuba
Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba.
, Calif. -- PLL PLL - phase-locked loop  Noise Analyzer(TM)'s Fast and Silicon-Accurate Analysis Enables Processor Start-Up To Meet Stringent Jitter A flicker or fluctuation in a transmission signal or display image. The term is used in several ways, but it always refers to some offset of time and space from the norm. For example, in a network transmission, jitter would be a bit arriving either ahead or behind a standard clock cycle  and Power Specifications

Berkeley Design Automation Inc., a provider of innovative silicon analysis tools for analog/RF and mixed-signal applications, today announced that P.A. Semi P.A. Semi is a fabless semiconductor company founded in Santa Clara, California 2003 by Dan Dobberpuhl who was the lead designer for the DEC Alpha and StrongARM processors. , a Silicon Valley startup developing the high-performance, low-power PWRficient processor family, has successfully deployed PLL Noise Analyzer on its 65nm processor chip. P.A. Semi was able to meet extremely demanding noise and jitter specifications on the processor's PLLs that run up to 2.5GHz, while optimizing for power and area using Berkeley Design's advanced circuit analysis technology.

"At P.A. Semi, we are designing high performance, power-efficient, multi-core processors that offer up to a ten-fold increase in performance per watt," said Sribalan Santhanam, vice president of engineering, Design Group, at P.A. Semi. "Our applications demand ultra-low noise and jitter for clocking and I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output.

I/O - Input/Output
, and Berkeley Design Automation's PLL Noise Analyzer enabled us to quickly and accurately analyze the noise and jitter of our 65nm PLLs."

"Noise analysis of circuits at 65nm is very complex," said Vincent von Kaenel, Director of Analog Engineering, P.A. Semi. "PLLs pose one of the biggest challenges due to the highly nonlinear nature of the circuit, coupled with the variability of the process. PLL Noise Analyzer enabled us to accurately analyze PLL noise and jitter and characterize the top noise contributors quickly before we taped out Refers to the completion of the design of a chip. The next stage is to put it into production. The term comes from the early days when designs were transferred to the fabricator via magnetic tape.  our 65nm PLLs. We successfully met our noise and jitter targets."

Berkeley Design Automation's PLL Noise Analyzer is based on next-generation circuit analysis technologies that allow designers to accurately characterize the noise and jitter performance of their designs before tape-out. Berkeley Design's proprietary Stochastic Nonlinear Engine(TM) is the foundation of PLL Noise Analyzer and it provides unprecedented analysis speed and accuracy. With the fast and accurate noise analysis provided by PLL Noise Analyzer, designers are free to confidently optimize their PLLs for area and power.

"We are very pleased that Berkeley Design's accurate noise analysis technology has enabled P.A. Semi to meet their very aggressive noise and power targets in their first tape-out," said Ravi Subramanian, President and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board.  of Berkeley Design Automation. "Our advanced silicon analysis technology was designed to address exactly these types of challenges. By providing speed and accuracy in these new analyses, we can accelerate the time-to-volume production of complex designs such as PA Semi's PWRficient processor."

About Berkeley Design Automation

Berkeley Design Automation Inc. was founded in 2003 to address the verification challenges in the design of next-generation high-performance analog/RF integrated circuits Integrated circuits

Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1.
 (ICs). Berkeley Design Automation is a venture-backed, private company funded by Woodside Fund and Bessemer Venture Partners Bessemer Venture Partners is a private venture capital firm with offices in Silicon Valley, New York, Massachusetts, China, and India. It has backed such companies as Ciena, Flarion, Parametric Technologies, Skype, Staples, VeriSign and Veritas. . The company's technology characterizes the nonlinear, time-varying behavior of complex analog and RF circuits, providing extremely accurate predictions that dramatically reduce the need for silicon re-spins. The company's first product, PLL Noise Analyzer, the industry's only noise analysis tool for phase-locked loops Phase-locked loops

Electronic circuits for locking an oscillator in phase with an arbitrary input signal. A phase-locked loop (PLL) is used in two fundamentally different ways: (1) as a demodulator, where it is employed to follow (and demodulate) frequency or
 (PLLs), has been adopted by semiconductor industry leaders. For more information, see http://www.berkeley-da.com.

About PLL Noise Analyzer

PLL Noise Analyzer fits easily into existing analog/RF verification flows. It reads HSPICE and Spectre format netlists and standard device models. PLL Noise Analyzer is available for Sun and Linux operating systems.

PLL Noise Analyzer and Stochastic Nonlinear Engine are trademarks of Berkeley Design Automation, Inc.

Berkeley Design is a registered trademark of Berkeley Design Automation, Inc. PWRficient(TM) is a trademark of P.A. Semi Inc.

HSPICE is a registered trademark of Synopsys Inc. Spectre is a registered trademark of Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services.

http://cadence.com/.

See also Verilog.
 Inc.
COPYRIGHT 2006 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2006, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

 Reader Opinion

Title:

Comment:



 

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Date:Jan 9, 2006
Words:594
Previous Article:SIGMA-C Delivers Precise Image-Aware DFM Product to Eliminate Expensive Design Iterations at 65nm and Below; Proven SOLID+ Micro-Lithography...
Next Article:95.9 KFSH-FM The Fish(R) Announces Fifth Annual FISHFEST(R) Sunday, March 26 at the Verizon Wireless Amphitheater.
Topics:



Related Articles
Military wireless systems require sturdier defenses. (Industry Viewpoint).(minimizing radio frequency interference)
Introducing Berkeley Design Automation - Delivering Next-Generation Analog/RF IC Verification Technology; Company's breakthrough technology...
THine Electronics Adopts Berkeley Design Automation's PLL Noise Analyzer(TM) For Design of Digital Consumer Multimedia ICs.
Berkeley Design Automation's PLL Noise Analyzer(TM) Accelerates Time-To-Volume; Precision Circuit Analysis(TM) Technology Enables Japan's Leading...
TRADE NEWS: Agilent Technologies Announces Breakthrough in Signal Analysis Performance for Current and Emerging Applications; Industry's Best...
TRADE NEWS: Agilent Technologies' Newest ENA Series RF Network Analyzer Sets De Facto Industry Standard in RF Network Analysis.
OMRON Develops UWB Antenna with Filter-Assist Functionality Optimized for WiMedia Alliance BandGroup 1; Selected for Use in Sigma Designs Windeo UWB...
TRADE NEWS: Agilent Technologies Introduces Ultra-Wideband Vector Signal Analyzer for Modulated Wideband Communications Signals.
Niigata-Seimitsu Adopts Full Suite of Berkeley Design Automation Tools.
CLK Design Automation Boosts Timing Analysis Performance By 10-100x With Debut of Amber Analyzer.

Terms of use | Copyright © 2009 Farlex, Inc. | Feedback | For webmasters | Submit articles