Optimizing stencil design for Pb-free SMT: in quantifying the impact of solder spread on typical SMT defects, the authors devised new apertures and a new test pattern.

The primary goal of stencil printing is to put the proper amount of solder in the proper location repeatably. The aperture size, shape and stencil thickness determine the amount of solder deposited, while the position of the aperture determines the location of the deposit.

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Methods of effectively controlling the position of the aperture have already been determined (1) and are reviewed here. The goal of this study was to determine the best size and shape of the aperture for lead-free solder pastes. It is generally accepted that lead-free solders do not wet or spread as readily as their Pb-bearing counterparts. This behavioral difference presents concerns for assemblers on several fronts: exposed copper (or substrate surface finish) near the perimeters of pads, different defect rates for mid-chip solderballs and tombstones.

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An experiment was designed to quantify the impact of different solder spread on typical surface-mount defects. Part I of the experiment baselined spread and defect rates for Pb-bearing and Pb-free pastes with aperture geometries traditional to Pb-bearing SMT. Part II attempted to optimize stencil apertures to improve upon the defect rates when using a Pb-free paste. In Part I, surface finishes included organic solderability preservative (OSP), electroless nickel-immersion gold (ENIG), immersion silver (ImAg) and immersion tin (ImSn). OSP and ImSn were used in Part II.

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Experimental Design

Wetting and spread. There are two methods for studying spread characteristics of solder pastes. The first involves printing a circular deposit of known area on bare metallic substrate, reflowing the sample and measuring the area covered with solder post-reflow. The ratio of the post-reflow area to that of the original printed area gives a measure of the spreading of the paste and an indication of wetting for the particular board finish on which it was measured. An alternative test involves printing pairs of uniform thickness (0.040") solder paste stripes onto an array of uniform thickness (0.030"), equally spaced traces on the board. The paste stripes have increasing gap sizes between them and are printed perpendicular to the traces.

During reflow the molten solder expands along the metal lines on the board. If there is enough spread, the gap between two adjacent solder spots is bridged. The gaps between solder paste stripes are varied from 0.1 mm to 0.8 mm, with a maximum of 20 bridges possible for each gap size. The number of gaps to bridge are counted and the results plotted as a function of the gap size.

Quad flatpacks. For devices with pitches under 0.020", the risk of solder bridges is increased when the aperture to pad ratio is 1:1. To reduce the risk of solder bridges the usual trick is to reduce the print area by certain amount. A 10% reduction in aperture area, known as aperture cropping, is common. However, the risk of exposed pad material increases when printing with a 10% reduction. Although exposed pad material has not been shown to present a reliability concern, it can present a cosmetic concern for some assemblers. If exposed pads are a concern with Pb-bearing paste, the concern is heightened with Pb-free paste due to its lower spread characteristics.

To quantify the impact of aperture cropping, two 0.020" pitch QFPs were assembled on each test vehicle. In Part I one of the QFPs had apertures at 1:1 with the pads; the other was reduced by 10%. In Part II both apertures were fixed at 1:1, 5% reduction and 10% reduction. Foils of 0.05" and 0.006" were used in both portions of the test. In total, four combinations of area and foil thickness were tested in Part I and six combinations were tested in Part II.

Mid-chip solder balls (MCSB) are also a common defect that can be impacted by stencil design. Although the formation of mid-chip balls can have many causes--pad design, soldermask relief, placement pressure, termination geometry and metalization, pad finish and reflow profile--the size and shape of the solder deposit will positively or negatively influence the formation of mid-chip balls.

If a (relatively) larger volume of solder paste is deposited on the pad, especially in the area where the chip will be placed, the placement of the chip will displace the soft paste. Any paste pushed under the body of the device may pull back to the pad during the reflow cycle, or it may not. If the solder does not pull back, it migrates to the side of the device through capillary action during its liquidus phase, forming a solder ball that solidifies upon cooling.

Data generated over hundreds of MCSB tests with Pb-bearing paste indicate that the worst case stencil design for MCSBs is a rectangular aperture with a 1:1 pad ratio and a 0.006" stencil foil. The best case is a "homeplate" design with a 10% area reduction on a 0.005" foil. Figure 1 illustrates the rectangular, homeplate and inverse homeplate designs. The historical data also indicate that a soak profile is less forgiving than a ramp profile, as the paste continues to soften and yield (hot slump) before reaching its liquidus temperature.

The MCSB tests included both the best and worst case stencil design scenarios. In Part I, for each surface finish, paste type and profile type (ramp and soak), 300 of each device size were assembled: 1206, 0805, 0603, 0402. We mounted 150 vertically, 150 horizontally. IPC-recommended pad geometries were used. The 0201 packages were not included in the study, as many of the principles that apply to the larger passives do not necessarily translate smoothly. The authors believe that 0201s should be studied separately in greater depth. (2)

In Part II, three new aperture designs were introduced. The first was a homeplate with the pointed end radiused. The second two were inverse homeplates with three corners radiused (Figure 2). Again, 300 of each component size were assembled, using two surface finishes, two stencil thicknesses and two profiles.

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Tombstones are another common SMT defect phenomena that, like MCSBs, have many factors that influence their formation, but can be impacted by stencil design. Tombstones, also referred to as the "drawbridge effect" or "Manhattan effect," occur when the surface tension of the solder acting on one termination is greater then the surface tension on the other termination. The uneven forces create a moment on the device that causes it to rise and stand on end like an open drawbridge.

Design factors that influence tombstoning include pad geometry and thermal relief. Assembly factors that influence tombstoning include positional accuracy of the paste deposit, placement accuracy and ramp rate entering the liquidus phase of the reflow cycle. Aperture design comes into play as it interacts with the other assembly factors: if the part is not placed on center, it is likely to contact more solder on one side of the termination than the other, which can then lead to uneven forces being applied to the component terminations as the solder melts. Historical data with SnPb solder indicate that some aperture geometries, like the rectangle, are more forgiving in this case, but others, like homeplates, are not.

[FIGURE 4 OMITTED]

As can be interpreted from the previous two discussions, stencil design parameters for tombstoning and mid-chip solder-ball appear to be exactly opposite of each other. In a real-world production, a compromise must be struck. The devices used to study midchip solder balling were also inspected for tombstoning. Although this study was not intended to minimize tombstones, the defect rates were monitored since the investigators did not want to optimize MCSB performance at the expense of tombstone performance.

A total of 174 circuit cards were assembled on a small laboratory production line. The equipment set used included an MPM UltraFlex 3000 stencil printer, an Advantis pick-and-place machine and an Electrovert OmniFlow seven-zone reflow oven with an air atmosphere. Reflow profiles are illustrated in Figure 3. Solder pastes used were Type 3, no-clean pastes. The Pb-bearing alloy was Sn63Pb37. The Pb-free alloy was Sn96.5Ag3.0Cu0.5 (SAC 305).

Results and Discussion

As described earlier, the spread test was performed in two different ways. The results showed that the spread of Pb-free and Pb bearing pastes is very close, with Pb-free spreading marginally more. These results are curious, as it is documented and generally accepted that Pb-bearing solders spread better than lead-free solders. Potential reasons for these anomalous data include both the nature of the test and the measurement method. Because the printed solder sample is much smaller than the pad it is printed on, the spread is not constrained by the edges of the pad. Uneven spread around the perimeter of the solder deposit is not accounted for. It is a simple area ratio calculation without consideration to form or flow of the solder. The areas are measured electronically, with human assistance in defining the measurement area. This brings a certain degree of subjectivity to the test, particularly if different people measure different specimens at different times.

The authors have harbored certain skepticism about the validity of this test method, which is why the cross-print test was introduced. The cross-print test yielded much better definition in the wetting results than the simple spread tests. Based on our study, the quantified difference in spread characteristics agrees clearly with what is known and accepted in the industry. As anticipated, ENIG finish showed complete spread even to the upper limit of the test and the ImSn showed similar behavior with only a few sites unbridged at the highest gap. Also as expected, OSP and ImAg showed lower spread characteristics both with Pb-bearing and Pb-free pastes. In the future, the authors will employ the cross-print test to characterize spread properties. Compared to its predecessor, this test method is more accurate, objective, faster and more economical to perform.

QFP wetting. QFPs were inspected for exposed pad material and solder bridges. A total of 348 QFPs were assembled and inspected. Only four solder bridges were found, and the authors are cautious about drawing conclusions based on such a small sample size and seemingly statistically insignificant results. Because the assembly process took place in the lab environment with well-tuned printing and placement equipment, the noise associated with a typical production environment was not present. The authors feel that the data would be more revealing if a larger sample size were created with the typical tolerances seen on production equipment. As expected, ENIG and ImSn showed full spread regardless of the aperture cropping, therefore it is suggested that assemblers currently cropping QFP aperture continue the practice when assembling onto ENIG or ImSn surface finishes. Also as expected, OSP and ImAg did not show complete spread to the toes of the pads but both met IPC acceptability standards. ImAg did show better spread than OSP at the toes but not as good as ENIG or ImSn.

Mid-chip solder balls. Mid-chip solder balls were counted for all the devices on the board. A total of 6,960 devices were populated and inspected. Figure 4 summarizes total MCSB counts. Observations include:

* Pb-free paste shows less number of MCSBs than the Pb-bearing paste in general.

* ImSn produced the least amount of MCSBs, followed by ENIG, OSP and ImAg.

* Soak reflow profiles produce more MCSBs than ramp profiles.

* Stencils of 0.006" produced far more MCSBs than 0.005" stencils. Note: The 0.006" foil was designed with rectangular apertures at 1:1 with the pad, and the 0.005" foil was designed with homeplate apertures with a 10% reduction, in order to benchmark best- and worst-case scenarios.

For Pb-free paste there appeared to be more MCSBs for the intermediate size devices (0603) especially for ImAg and ENIG board finishes. For OSP and ImSn they appeared more evenly distributed. For Pb-bearing pastes the number of MCSBs observed in general decreased as device size decreased, with the only exception being the ImAg board finish in which MCSB rates appeared to spike on 0603 devices. Of the 72 MCSBs recorded for ImAg, 67 were observed on two assemblies that ran sequentially; one of these two boards also had 28 MCSBs on the vertically placed parts. The investigators suspect that there are anomalous data with a special cause, most likely related to placement. Nevertheless, the data were included in the final tallies and report; the reader may wish to discount them. In Part II, three new apertures were studied. The radiused inverse home plate with proportions of 20%, 60% and 20% produced the least amount of mid-chip solder balls.

Tombstoning. In general the number of tombstones observed was very small. Observations include:

* Pb-free paste generally showed higher level of tombstoning defects compared to Pb-bearing, most likely attributable to better wetting behavior of the latter.

* Interestingly, the soak profile showed a higher level of tombstoning defects. This contradicts some beliefs that high soak profiles can limit tombstones.

* Stencil foils of 0.006" produced greater amounts of tombstones than 0.005" foils, most likely due to the higher volumes of solder. The authors believe the next study should correlate printed volumes to tombstoning rates, and include 0.004" foils.

* The radiused inverted home plate aperture design that used the proportions 20/60/20, which was found to minimize MCSBs, produced no tombstones in this study. The authors would like to stress the fact that this test was not designed to characterize tombstoning behavior, but to ensure that aperture optimization for MCSBs did not dramatically increase tombstoning rates. The effect of placement accuracy and profile type on tombstoning is so great that this study would have to be expanded beyond reasonable limits if it were to include placement and reflow parameters.

The positional accuracy of the stencil's apertures and the method by which they are aligned to the PCB pads determine the location of the paste deposit. To control positional accuracy, stencil manufacturers must characterize their laser cutters and then calibrate them using offsets learned through the characterization process. One method of characterizing stencil manufacturing process is to design a standardized test vehicle, cut it, and measure the variation from CAD data, or nominal position. The test vehicle used at Cookson Electronics is comprised of 324 identical circular apertures set on 1" centers over a 17 X 17" grid. After cutting and measuring, the data are analyzed for linear drift along the length of the machine axes and for angular displacement. The results of the analysis are then used to incorporate correction factors to ensure that positional accuracy is held to 0.001" at 4 sigma levels, or a Cpk of 1.33 (Table 1).

Several sources that affect the stencil-PCB alignment variation include the variation of the positional accuracy of the PCB, the variation of the alignment capability of the printer and the variation in the stencil itself. The PCB variation is by far the largest contributor to misalignment.

PCBs are known to "shrink" from CAD data as a result of their fabrication process. They also experience some shrink in their first reflow process, exacerbating the misalignment when printing the second side of the board. To address variation in the PCB, it can be measured so that a stencil can be generated to custom-fit the PCBs.

Recommendations

The optimum apertures found for minimizing the formation of mid-chip solder balls is the radiused inverted homeplate design with aperture proportions of 20%/60%/20%. This aperture did not produce any tombstones.

To gauge wetting and spread capability of solder pastes, the cross-print pattern was found to be superior to the spread ratio test. QFP data were inconclusive. It is recommended that this type of test be performed in production environments to capture a greater sample size the systemic noise associated with high volume manufacturing operations. Further studies are recommended to characterize tombstone behavior, particularly with different lead-free alloys.

Table 1: Correlation of process capability to position accuracy of [+ or
-]0.001"

Alloy      Profile      Ramp Rate        Soak     Soak     Peak Temp
                                         Time     Temp

Tin-Lead    Ramp    1.5[degrees]C/sec      -        -     215[degrees]C

            Soak    1.25[degrees]C/sec  120 sec  150-170  215[degrees]C

Lead-Free   Ramp    1.5[degrees]C/sec      -        -     240[degrees]C
(SAC305)
            Soak    1.25[degrees]C/sec  120 sec  160-190  240[degrees]C

Alloy      Time Above   Time to
           Liquidus    Peak Temp

Tin-Lead     45 sec     130 sec

             48 sec     276 sec

Lead-Free    58 sec     148 sec
(SAC305)
             55 sec     314 sec

Note: PPM Defective is based on a static process and does not include
the 1.5 sigma shift.

Acknowledgments

The authors wish to recognize the investigational team that performed and supported this study: Westin Bent, Grant Burkhalter, Leon Herbert, Horladine Maciel, Bawa Singh, Valentijn Van Velthoven and Greg Wade.

Ed.: This article was first published at SMTA International, September 2004, and is reprinted here with permission.

References

(1.) C. Shea, V. Van Velthoven, R. Tripp and R. Pandher, "Reducing Variation Through 'Intelligent' Stencils," Circuits Assembly, September 2004.

(2.) A. Teredesai, S. Aravamudhan, J. Belmonte and R. Szymanowski, "Self-Centering of Offset Chip Components in a Pb-free Assembly," IPC Apex Proceedings, February 2004.

(3.) J. Smetana, B. Horsley, J. Lau, K. Snowdon, D. Shangguan, J. Gleason, I. Memis, D. Love, W. Dauksher and B. Sullivan, "HUPUG's Lead-Free Design, Materials and Process of High Density Packages," IPC Apex Proceedings, March 2003.

(4.) D. Geiger, F. Mattsson, D. Shangguan, M.T. Ong, P. Wong, M. Wang, T. Castello and S. Yi, "Process Characterization of PCB Assembly Using 0201 Packages with Lead-Free Solder," Nepcon West/Fiberoptic Expo, December 2002.

Ranjit S. Pandher is senior scientist and Chrys Shea is manager of R&D applications engineering at Cookson Electronics Assembly Materials (cooksonelectronics.com); [e-mail].