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OneSpin Solutions Delivers Next-Generation Equivalence Checker for Advanced FPGA Design Verification.


360 EC-FPGA First to Support All Sequential Optimizations Performed by FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market.  Synthesis Tools on Large Designs

MUNICH, Germany & SUNNYVALE, Calif. -- OneSpin Solutions GmbH, an electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) company that provides breakthrough formal verification
"Verifiability" redirects here. For the Wikipedia policy, see Wikipedia:Verifiability.


In the context of hardware and software systems, formal verification
 solutions, today announced its next-generation 360 EC-FPGA equivalence checking solution. It is the industry's first equivalence checker check·er  
n.
1.
a. One, such as an inspector or examiner, that checks.

b. One that receives items for temporary safekeeping or for shipment: a baggage checker.

2.
 to support all sequential optimizations performed by FPGA synthesis tools on large designs, enabling designers to meet functional, performance and cost targets, with minimal manual intervention. It is ideal for both prototyping and production-part verification.

The new 360 EC-FPGA enhances OneSpin's established 360 EC ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor.  equivalence checker with innovative FPGA verification capability. It thoroughly proves, without simulation, that design functionality is maintained through all implementation phases of FPGA and ASIC design.

Unlike other established equivalence checkers, synthesis-tool-independent 360 EC-FPGA allows FPGA designers to leverage the optimizations afforded by FPGA synthesis tools and to verify the design "as is," without having to switch off optimizations and undertake extensive manual scripting. In particular, it verifies whole-chip flat netlists, enabling the most aggressive optimizations. It works with established FPGA synthesis tools and flows without any change to the flow, delivering industry-leading ease of use. Moreover, the solution does not require the "side files" generated by the synthesis tool, which often are not even validated by equivalence checkers.

According to according to
prep.
1. As stated or indicated by; on the authority of: according to historians.

2. In keeping with: according to instructions.

3.
 Peter Feist feist   also fice
n. Chiefly Southern U.S.
A small mongrel dog.



[Variant of obsolete fist, short for fisting dog, from Middle English fisting,
, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board.  of OneSpin, "Our customers tell us their ability to use the 360 EC-FPGA means they don't have to trade-off quality vs. productivity. Our new push-button (electronics) push-button - A roughly fingertip-sized plastic cover attached to a spring-loaded, normally-open switch, which, when pressed, closes the switch. Typical examples are the keys on a computer or calculator keyboard and mouse buttons.  approach accelerates hardware delivery and software development, speeding overall time to market."

The 360 EC-FPGA solution verifies functional equivalence between the register transfer level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) code and the post-synthesis FPGA netlist, as well as between the post-synthesis netlist and the post-place-and-route FPGA netlist. The new equivalence checker supports all major FPGA families from Altera and Xilinx, including netlists generated by the ubiquitous Synplicity([R]) Synplify Pro([R]) and the Altera([R]) Quartus([R]) II synthesis flows.

"OneSpin's 360 EC-FPGA shows deep understanding of the sophisticated optimizations performed by Synplicity's FPGA synthesis tools," said Andy Haines, Synplicity's Senior VP of Worldwide Marketing, "bringing extra productivity to our mutual customers."

Majid Ghameshlu, Senior Project Manager Chip Design at Siemens CES added, "360 EC-FPGA secures our FPGA prototyping flow from bugs that might be introduced during synthesis and optimization steps. Its extensive support for sequential optimizations allows us to use more sophisticated synthesis optimizations, resulting in a faster implementation and in better device utilization. 360 EC-FPGA has proven very useful in shortening our debugging (programming) debugging - The process of attempting to determine the cause of the symptoms of malfunctions in a program or other system. These symptoms may be detected during testing or use by real users.  cycle."

The 360 EC-FPGA solution also can be deployed with OneSpin's 360 Module Verifier (360 MV) to deliver error-free FPGA-based intellectual property from RTL to FPGA device. The 360 MV static formal verification solution ensures error-free IP, while 360 EC-FPGA preserves this quality through subsequent design phases.

Pricing and Availability

The 360 EC-FPGA solution - featuring FPGA equivalence checking for Synplicity's Synplify Pro and Altera's Quartus II Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs.

Quartus II enables the developer to compile their designs, perform timing analysis, examine RTL diagrams and configure the target device with the programmer.
 FPGA synthesis tools as well as ASIC equivalence checking - is available now. A license is priced at U.S. $ 137,500.

ABOUT ONESPIN SOLUTIONS

OneSpin Solutions provides electronic design automation (EDA) methodologies, tools and services for fundamental verification tasks at transaction, RT and gate levels. OneSpin's patented formal verification technology builds on 250 engineer-years of innovation and development, and has been field-proven on hundreds of complex designs to increase the quality of results, while reducing the cost and time to results. Market-leading consumer, telecommunications, automotive, computer, and embedded system Any electronic system that uses a CPU chip, but that is not a general-purpose workstation, desktop or laptop computer. Such systems generally use microprocessors, or they may use custom-designed chips or both.  companies rely on OneSpin's technology to achieve true functional sign-off for their IP, complex subsystems, processors and peripherals, and to preserve this quality level through subsequent design phases. Privately held, OneSpin was founded in 2005, and is headquartered in Munich, Germany. For further information please visit http://www.onespin-solutions.com/ or email info@onespin-solutions.com. Contact: OneSpin Solutions GmbH, Theresienhoehe 12, D-80339 Munich, Phone: + 49-89-99013-0; and 1275 Orleans Drive, Sunnyvale, CA 94089, Sunnyvale, CA 94089, Phone: 408.470.4970, Fax: 408.904.7515.

OneSpin Solutions and the OneSpin logo are trademarks of OneSpin Solutions GmbH. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
COPYRIGHT 2007 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2007, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Date:Feb 12, 2007
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