ON Semiconductor Introduces Precise ECL Timing Delay Chip For High-Frequency Clock Management.Business Editors & High-Tech Writers PHOENIX--(BUSINESS WIRE)--Oct. 28, 2002 MC100EP196 offers unparalleled PECL/NECL delay-programmability for clock management within high-performance test, instrumentation and networking applications Extending its presence in the high-performance clock- and data-management arena, ON Semiconductor (Nasdaq:ONNN) today introduced the MC100EP196 -- an Emitter Coupled Logic Emitter Coupled Logic - (ECL) (Or "Current Mode Logic") A technology for building logic gates where the emitter of a transistor is used as the output rather than its collector. ECL has a propagation time of 0.5 - 2 ns (faster than TTL) and a power dissipation 3 - 10 times higher than TTL. (ECL (Emitter-Coupled Logic) A digital circuit composed of bipolar transistors in which the emitter ends are wired together. ECL gates switch faster than TTL gates, but consume more power. See TTL, I2L and bipolar. 1. ) programmable delay chip with a secondary tuning input for clock de-skew in networking systems, pattern generation, and pulse and data formatting in test and instrumentation equipment. As semiconductor components move toward higher frequencies, the current level of precision of standard delay devices is insufficient for controlling the timing signals in advanced networking systems. Designers now struggle with the skew between timing signals that is created by topological differences in circuit board as the period of signal arrival decreases. Test-and-measurement of these high-performance systems also demand equipment capable of near-ideal signals at a much higher frequency. The MC100EP196 addresses these critical design needs. At operating frequencies greater than 1.2 gigahertz (GHz), the MC100EP196 offers the same high performance of the MC100EP195 -- a 3.3 volt (V), 5 V ECL programmable delay chip -- with delay timings between 2.2 and 12.2 nanoseconds (ns) in 10 picoseconds (ps) units. A fine tune (FTUNE) input feature added to the MCP (1) See Microsoft certification. (2) (MultiChip Package) A chip package that contains two or more chips. It is essentially a multichip module (MCM) that uses a laminated, printed-circuit-board-like substrate (MCM-L) rather than ceramic (MCM-C). 100EP196 delivers supplementary delay programmability between 0 ps and 60 ps to address the increased accuracy required by the latest high-speed applications. This expanded programmability eliminates the need to re-spin, re-assemble and re-test circuit boards if the timing signals do not match. The MC100EP196 accepts ECL, Complimentary Metal Oxide Semiconductor See MOS. (electronics) Metal Oxide Semiconductor - (MOS) The three materials used to form a gate in the most common kind of Field Effect Transistor - a MOSFET. (CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. ) and Transistor-Transistor Logic (TTL (1) (Time To Live) A parameter in a network packet that sets a time limit to its validity. In order to prevent an IP packet from propagating endlessly through the network, the value in the TTL field is reduced by each router. ). This provides system designers with the ability to directly program the MC100EP196 from a micro-controller, thus eliminating the need for specific programming circuitry. The MC100EP196 is compatible with both positively- and negatively-referenced low voltage 3.0 V to 3.6 V system supplies in PECL PECL PEAR (PHP Extension and Application Repository) Extended Code Language PECL Principles of European Contract Law PECL Positive Emitter Coupled Logic PECL Pseudo-Emitter Coupled Logic PECL Positive-Referenced Emitter Coupled Logic or NECL NECL Nectin-Like Protein NECL Negative Emitter Coupled Logic NECL Nonepitheliotropic Cutaneous Lymphosarcomas mode respectively. Required delay is selected by the 10 programmable data select inputs D(0:9) that are latched in place by a high-signal on the latch enable (LEN (Low Entry Networking) In SNA, peer-to-peer connectivity between adjacent Type 2.1 nodes, such as PCs, workstations and minicomputers. LU 6.2 sessions are supported across LEN connections. ) control. ON Semiconductor that increases the programmable range even further by offering the MC100EP196 with an additional pin for cascading multiple devices.. "The overall performance and versatility of the MC100EP196 provides an ideal way to overcome three primary design hurdles," said Mike Radhanauth, ON Semiconductor market development director for High Frequency Products. "With the MC100EP16, systems designers can effectively de-skew incongruent in·con·gru·ent adj. 1. Not congruent. 2. Incongruous. in·con gru·ence n. clock signals, perfect the generation of test pulses and format Automated Test Equipment (ATE) data." Packaging and Price Packaged in a space-saving standard 32-pin Low Profile Quad Flat Pack (LQFP See QFP. ), ON Semiconductor offers the MC100EP196 for $9.40 per unit in 10,000 unit quantities. The device is also available in wafer form for designers requiring additional design flexibility. For additional technical information visit http://www.onsemi.com/tech. About ON Semiconductor ON Semiconductor offers an extensive portfolio of power- and data-management semiconductors and standard semiconductor components that address the design needs of today's sophisticated electronic products, appliances and automobiles. For more information visit ON Semiconductor's Web site at http://www.onsemi.com. ON Semiconductor and the ON Semiconductor logo are registered trademarks of Semiconductor Components Industries LLC. All other brand and product names appearing in this document are registered trademarks or trademarks of their respective holders. Although the company references its Web site in this news release, such information on the Web site is not to be incorporated herein. |
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