OFFIS/OSC Announces New Version of First Tool for Optimizing Chip Power Consumption at the Highest Level of Abstraction.

Business Editors/High-Tech Writers

OLDENBURG, Germany--(BUSINESS WIRE)--March 4, 2002

ORINOCO(R) 2002.1 Now Features Interconnect and Controller Power

Estimation from C/C++ Specifications and Improved Accuracy

OFFIS Systems and Consulting GMBH (OSC), today announced a new version of ORINOCO(R), the industry's only design tool for optimizing chip power consumption at the specification level, offering up to 75% power reduction and decreasing design cycle time from weeks to minutes over Register Transfer Level (RTL). Developed out of several research projects by the embedded systems division of OFFIS, ORINOCO(R) 2002 allows efficient analysis and optimization of complex chips at the earliest possible stage in the design process where significant improvements can be made in performance, power and productivity gains. The new version of ORINOCO(R) analyzes system specifications written in C/C++ and for the first time, supports both interconnect and FSM (finite state machine) controller power estimation and power prediction for datapath components, clock trees, registers and memories. Controllers manage the functions and data transfers within a chip. Additionally, the accuracy of power estimations has been enhanced for a larger application domain and a broader range of target architectures including mobile multimedia applications.

"Many communication companies have encouraged us to work on the specification level, because it is the critical phase of system definition which has most impact on the system performance, cost and power consumption," said Dr. Wolfgang Nebel, professor for VLSI and embedded system design and vice chairman of OFFIS. "ORINOCO(R) is the result of many years of research and now enables the system designer to quickly evaluate the consequences of his decisions. Optimizing signal processing algorithms, memory structures and system architectures for low power is possible now very efficiently!"

"With the addition of interconnect and controller power, ORINOCO(R) 2002 covers all aspects of ASIC power consumption," said Massimo Bombana, senior EDA (Electronic Design Automation) specialist at Siemens ICN. "On the basis of our evaluation, we believe the innovative features of ORINOCO(R) effectively address design space exploration in terms of power, providing useful relative comparisons among different architectural choices that can later be synthesized manually or using Behavioral Compiler or similar tools."

Another senior engineer at Alcatel said, " ORINOCO(R) fits seamless into our design environment and tool flow, and the performance and stability of its power estimation capabilities are exceptionally good. The graphical representation provided by ORINOCO(R) 2002 provides easy viewing and intuitive analysis of data with accurate and detailed documentation, affording us a greater opportunity for significant savings in power consumption and designer productivity.

About ORINOCO(R)

ORINOCO(R) enables designers to visualize power consumption trade-offs at the specification level, the critical design phase where the opportunity for power optimization strongly increases. With minimal design intervention, ORINOCO(R) considers all possible algorithmic states and calculates corresponding maximum and minimum power values, eliminating unnecessary and time-consuming design iterations. ORINOCO(R) can be integrated with high-level synthesis tools to create power optimal architectures.

New Features in ORINOCO(R) 2002.1

ORINOCO(R) 2002.1 features major advancements for tackling the power problems associated with the shrinking die geometries and increased operation frequencies of deep submicron design. New features include:

-- Power estimation controller support. The steering unit within a design, the
controller manages the functions and data within the pathway of the chip. Never
before possible with other design tools, the power estimation of controllers
offers a significant advantage in battling the complex signal compression,
coding and filtering algorithms of advanced multimedia applications.

-- Improved wire length model. As chip complexity has grown, the need for
analyzing interconnect and wiring power consumption has become critical to the
functionality, performance and cost a chip. ORINOCO(R) now performs global
floorplanning at the specification level and considers all possible allocated
modules and the signal activity driving power consumption. ORINOCO(R) then
performs a global routing estimate for individual wires, providing a
high-quality and fast estimate of the interconnect power.

-- Improved Graphical User Interface for enhanced usability with intuitive tool
flow guide, improved configuration wizards and online manual.

-- A project-oriented approach for managing specific settings that are shared
by design groups. With ORINOCO(R) 2002, designers can easily switch between
different designs or different versions of the same design, enabling them to
explore different design alternatives much quicker.

-- Easier IP support for multiple Component Data Bases (CDBs) or libraries of
characterized IP components, allowing designers to use different libraries
(from different vendors) within one design, or compare the power efficiency of
different silicon libraries for a particular design.

-- State-of-the-art scheduling including time and resources constraints for
increased accuracy of design predictions and assumptions.

Pricing and Availability

ORINOCO(R) is currently in beta testing; a production version is expected to be available in Q2, 2002.

About OFFIS

Established in 1991, OFFIS is a research institute that concentrates on central issues of quality assurance and improved processes in the areas of microelectronics, embedded systems, healthcare, information and communication systems, and multimedia and Internet information services. OFFIS employs 150 people including 90 full time scientists, 40 of which are working on embedded system methodology and tools. To find out more about OFFIS, visit www.offis.de and www.lowpower.de.

About OSC

Established in 1999, OFFIS Systems and Consulting GMBH (OSC) is a commercial spin-off of OFFIS, an internationally renowned research institute. Because of its close links to the research institute, OSC combines leading edge technology know-how with a commitment to aggressively enter the market in its expert areas, currently focusing on business applications, geographical information systems and embedded systems. OSC's embedded systems LOW POWER-technology is developed in cooperation with OFFIS and patent rights are pending. OSC is rapidly growing and employs some 40 engineers. Along with ORINOCO(R), OSC offers Statemate MAGNUM(R), a verification and model checking tool marketed by I-Logix, Inc. To find out more about OSC, visit www.o-s-c.de and www.lowpower.de.

Note to Editors: ORINOCO is a registered trademark of OFFIS. Statemate MAGNUM is a registered trademark of I-Logix, Inc.