Novel wafer cleaning technologies to support advances in the semiconductor industry.

Demand for new and improved front-end semiconductor manufacturing technologies such as wafer cleaning and thin layer deposition is expected to stem from the rapid advancements in the integrated chip (IC) industry.

"Innovative wafer cleaning technologies, in particular, are crucial to meet the needs for finer fabrication, higher integration densities, and faster speeds of shrinking device features that support greater functionalities," observes Frost & Sullivan Research Analyst Sivakumar Muthuramalingam.

Moreover, new processes and technology solutions in wafer cleaning have become essential to meet the International Technology Roadmap for Semiconductors (ITRS) requirement for reduced surface contamination in the form of foreign metals, micro-roughness, watermarks, and silicon loss.

"Presence of these foreign objects and contaminants degrade the device quality and reliability--ultimately affecting the overall device yield," says Muthuramalingam.

While silicon wafer/substrate wafer cleaning is the most widely accepted solution for mainstream chip manufacturing due to its robustness and its feature of being a risk-free process, sub-100nm technologies require non-etching and damage-free techniques for precise interface control.

Non-liquid wafer cleaning techniques such as supercritical CO2 (ScCO2) are under development and show great promise as mainstream cleaning processes due to their high density, low viscosity, and negligible surface tension.

ScCO2 is likely to provide the semiconductor industry with an integrated solution for the post-etch residue cleaning and the drying of porous low-k materials. It is flexible since it uses specialty additives to target specific applications such as photo resist image collapse prevention, next-generation lithography photo mask cleaning, and particle removal.

In the deposition industry, advances in separation by implantation of oxygen (SIMOX), atomic layer deposition (ALD) for advanced nodes, and plasma source ion implantation (PSII) are expected for meeting the specific needs of sub-100 nm devices.

With regard to the SIMOX technology, the relatively immature state of modeling silicon-on-insulator (SOI) devices poses a significant challenge. Researchers are currently developing refined metrology tools to address this issue.

While there have been significant advancements in wafer cleaning and thin layer deposition, these techniques must demonstrate tangible advantages over the prevalent competing technologies for quicker acceptance in the market.

Proper cooperation with manufacturing equipment suppliers and circuit designers is critical to select the appropriate applications that fully exploit the uniqueness of the technology.

Further, the success of commercializing these next-generation manufacturing equipment and technologies depends on the quantum of applied and product-oriented research.

"The continual advancements in front-end semiconductor manufacturing depends not only on equipment design and improvements, but also on the development of innovative materials and associated processing that defines the overall device circuitry," concludes Muthuramalingam.