Novas Extends Support for Synopsys' Vera Testbench Automation Tool with New Testbench Debug Capabilities.Business Editors/High-Tech Writers SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--Feb. 16, 2004 Debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. Leader Provides Unified Debug of HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. Designs, Vera Testbenches and OpenVera Assertions Novas Software Novas Software was founded in 1996 by Dr. Paul Huang to address the ongoing problem of debugging chip designs. Since then, Novas has grown to employ over 130 people with office locations across the world including Texas, New Hampshire, the United Kingdom, Japan, Korea, India, , Inc., the leader in debug systems for complex chip designs, today announced full debug support for Synopsys' Vera(R) testbench automation tool with Novas' new nBench(TM) capability, a core component of its unified design and testbench debug solution. nBench enables the seamless debug of Vera testbenches and OpenVera assertions (OVA) with Verilog, SystemVerilog, VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. and mixed-language system-on-a-chip designs. Engineers can now trace cause-and-effect relationships across all design, assertion and testbench source code developed in Vera. This makes it much easier for them to fully comprehend design and testbench behavior using a single debug environment. (See February 16, 2004 press release, "Novas Announces Industry's First Unified Design, Assertion and Testbench Debug Solution.") "Today's announcement is a significant milestone that delivers on the promise of integrated design The introduction to this article provides insufficient context for those unfamiliar with the subject matter. Please help [ improve the introduction] to meet Wikipedia's layout standards. You can discuss the issue on the talk page. and testbench debug for SoC designers," said Dave Kelf, vice president of marketing at Novas. "We see an increasing demand for Synopsys' Vera testbench solution, and the integration of an interactive debug environment will further unify design and verification efforts." "Unification of tools and methodology is critical to addressing customer verification challenges," said Farhad Hayat, vice president of marketing, Verification Group at Synopsys, Inc. "Novas' commitment to supporting the Vera testbench automation tool and SystemVerilog language will complement the Synopsys Discovery(TM) Verification Platform and provide designers with a flexible, streamlined verification solution." About Novas Novas is the pioneer of debug systems that reduce functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, costs for complex integrated circuit and system-on-chip designs. Its market-leading Verdi(TM) and Debussy(R) Debug Systems, along with the Reusner(TM) Design Knowledge Publisher, go far beyond waveforms to help engineers understand and analyze complex or unfamiliar design behavior and share knowledge across global organizations. They cut by half or more the time it takes to locate, isolate and solve the root causes of design and verification problems. Novas is ranked first in customer satisfaction for the second consecutive year in a comprehensive EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. study published by CMP CMP (cytidine monophosphate): see cytosine. (1) (CMP Media LLC, Manhasset, NY, www.cmp.com) Part of United Business Media, CMP is a leading integrated media company that offers a wide variety of publications and services in the information . There are more than 12,000 Novas systems installed worldwide by over 400 companies and 35 EDA companies utilizing Novas technology in their products today. Novas is headquartered in San Jose, Calif. with offices in Europe, Japan and Asia-Pacific. For more information, visit www.novas.com or email info@novas.com Debussy is a registered trademark, and nBench and Verdi are trademarks of Novas Software, Inc. All other trademarks or registered trademarks are the property of their respective owners. |
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