New video networking chips use high-performance memory controller cores from Denali.Denali Software recently announced that its Databahn(TM) memory controllers have been licensed and successfully implemented in two new chips from ViXS: XCode--a content-secured multi-stream real-time transcoding chip; and Matrix--an IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 802.11a compliant baseband processor optimized for Rate-Range-Resilience and video delivery over IP networks. ViXS, the leading developer of end-to-end solutions for digital video networking, developed the two chips as part of an IP-based video distribution system with applications that include QoS delivery of broadcast quality video to clients like PCs, TVs & PDAs. XCode has already begun production ramp, while Matrix is set for sample by Q4 2002. "Our Databahn memory controller solution offers high performance coupled with complete configurability to handle a very wide range of application requirements," said Kevin Silver, Vice President of Marketing at Denali. "ViXS is a great customer; they have some very exciting product applications with unique and demanding memory system requirements. We are very pleased to be a part of two successful chips with them." "Denali has established a deep domain expertise in memory system design and verification," said Hugh Chow, Co-Founder/Vice President of Engineering at ViXS. "Memory system performance is critical to our application. By working with Denali, we were able to configure their Databahn memory controller core to perform exactly as required by our system design. Denali's support was also a key for the swift time-to-market of our product." The two ViXS chips incorporate a 64bit memory interface to DDR-SDRAM DDR-SDRAM - Double Data Rate Random Access Memory . The Databahn memory controller is configured for 166MHz operation (333MHz data transfers), provides ECC (1) (Error-Correcting Code) A type of memory that corrects errors on the fly. See ECC memory. (2) (Elliptic Curve Cryptography) A public key cryptography method that provides fast decryption and digital signature processing. (Error Correction Code Noun 1. error correction code - (telecommunication) a coding system that incorporates extra parity bits in order to detect errors ECC telecommunication - (often plural) the branch of electrical engineering concerned with the technology of electronic ), and supports various memory device configurations of up to a total of 256MB. The DDR (Double Data Rate) Refers to an SDRAM memory chip that increases performance by doubling the effective data rate of the frontside bus. For more details, see SDRAM. DDR - Double Data Rate Random Access Memory sequencer was tested and fully functional using state-of-the-art DDR parts of both 128Mb and 256Mb. The Databahn solution enables customers to configure a memory controller to match the exact application for the ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. in order to achieve 100% bus utilization. Customization is supported by an online infrastructure at Denali's eMemory.com site where a browser-based GUI (Graphical User Interface) A graphics-based user interface that incorporates movable windows, icons and a mouse. The ability to resize application windows and change style and size of fonts are the significant advantages of a GUI vs. a character-based interface. enables fast efficient configuration of various performance and interface options. To ensure compatibility with all the latest high-speed DRAM memory technologies, the configuration process is tightly integrated with a database of more than 4000 memory components, including the latest DDRII-SDRAM, DDR-SDRAM, FCRAM FCRAM Fast Cycle Random Access Memory FCRAM Fast Cycle Ram , and RLDRAM (storage) RLDRAM - (Reduced Latency DRAM) A kind of dynamic random access memory. RLDRAM comes in "common IO" and "separate IO" configurations. It supports broadside addressing. It is typically used in networking gear and set-top boxes that require high bandwidth memory. devices. The configuration process creates a machine readable specification file that drives the generation of the RTL from a single Verilog code base, which can then be simulated online to validate performance. Once the performance targets are met, other deliverables are generated, including verification routines, synthesis scripts, static timing analysis scripts, and documentation. The Databahn IP is library independent and covers solutions from .18u to .11u technologies, and DRAM device frequencies from 100-250MHz (200-500MHz data rate). |
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