New processor core family introduced by MIPS.
MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. (C)1995-2009 M2 COMMUNICATIONS http://www.m2.com
MIPS Technologies Inc (Nasdaq:MIPS) has introduced a new processor core family, the provider of industry-standard processor architectures and cores said on Monday.
According to the company, the new MIPS32 M14K and M14Kc cores are the first MIPS32-compatible cores that also execute the new microMIPS instruction set architecture (ISA (1) (Instruction Set Architecture) See instruction set.
(2) (Interactive Services Association) See Internet Alliance.
(3) (Internet Security and Acceleration) See .NET. ). The microMIPS ISA maintains 98% of MIPS32 performance while reducing code size by 35%.
The M14K core achieves performance of 1.5DMIPS/MHz and 180MHz in 130nm. It offers advanced features that are optimised for MCU (1) (MicroController Unit) A computer on a single chip. See microcontroller.
(2) (Multipoint Control Unit) A device that is used to moderate a videoconference of three or more end points (users at computers or groups of users and real-time embedded applications, including reduced interrupt latency, flash acceleration, debug features including iFlowTrace and support for AHB Lite as the interconnect interface. The core is configurable and extendable, offering a wide range of implementation options to lower cost and increase reusability.
The M14Kc core builds on the base M14K core with additional features for embedded applications such as home entertainment, home networking and personal mobile entertainment. The applications require a compact footprint but also the ability to execute complex software algorithms on an RTOS (1) (RealTime Operating System) An operating system designed for use in a real time computer system. See real time system, embedded system, process control and OS-9. or Linux. Based on the MIPS32 4KEc micro-architecture, which provides a powerful Linux and Java engine and improved performance for the Android An open platform for cellphones from the Open Handset Alliance (OHA). Based on Linux, Android includes a library of Java classes for building mobile applications.
Android and GPhone platform, the core has a full cache controller and translation lookaside buffer A Translation Lookaside Buffer (TLB) is a CPU cache that is used by memory management hardware to improve the speed of virtual address translation. A TLB has a fixed number of slots containing page table entries, which map virtual addresses onto physical addresses. (TLB) memory management unit (MMU).
The new cores are based on the new microMIPS ISA that offers 32-bit performance with 16-bit code size for most instructions. The microMIPS ISA combines recoded and new 16- and 32-bit instructions to achieve a balance of performance and code density. It incorporates all MIPS32 instructions and Application Specific Extensions (ASEs) including MIPS-3D ASE (Adaptive Server Enterprise) A relational DBMS from Sybase that runs on Windows NT/2000, Linux and a variety of Unix platforms. ASE is a comprehensive and robust data management product with a long history dating back to the late 1980s. , MIPS DSP ASE, MIPS MT ASE and SmartMIPS ASE, as well as new instructions for advanced code size reduction.
The company also said it is providing complete software development tool support for the new cores, with the Eclipse-based MIPS Navigator Integrated Component Suite (ICS (1) (Internet Connection Sharing) A Windows feature that enables two or more computers to share one Internet connection. First introduced in Windows 98 Second Edition, sharing is accomplished with network address translation (NAT), which is the common method. ) and System Navigator probes for debugging. MIPS Technologies is also working with third party software vendors for tool and OS support.
The new M14K and M14Kc cores will be available in Q1 2010. No pricing details were disclosed.
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