New Synopsys Synthesis Technology Boosts ASIC Performance 15 Percent.

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--March 11, 1996-- Synopsys, Inc. (NASDAQ:SNPS) today introduced innovative behavioral synthesis technology that improves ASIC performance by more than 15 percent, according to benchmarks on register-transfer-level (RTL) designs.

The new Behavioral Retiming (BRT) capability is part of Synopsys' Behavioral Compiler product -- the next generation of synthesis.

"The industry shift to behavioral design has started because it significantly improves designer productivity," said Penny Herscher, vice president of the Design Environment business unit at Synopsys.

"With Behavioral Retiming, today's designers who haven't yet made the transition from RTL to behavioral design methodology can still build significantly faster chips without changing the way they design. This parallels the transition designers made from schematic capture to RTL in the early 1990s. Compelling improvements in quality of results continue to be the key."

Synopsys Breakthrough Targets Broad Application, Ease-of-Use

Retiming is a behavioral technique that moves registers in a design to optimal locations without affecting the control logic. BRT performs sequential optimization on the registers which have been explicitly defined and fixed by the designer in an RTL design. Although it can be applied to designs created from the outset using behavioral methodology, BRT is specifically targeted to and has the greatest impact on RTL designs.

To date, retiming has been commercially viable in only the simplest of cases because of the polynomial compute complexity associated with solving the problem. Breakthrough research conducted by Synopsys Fellow Richard Rudell and other researchers has led to algorithms that reduce the retiming problem to near-linear complexity. As a result, Synopsys' BRT can now be applied to a broad range of high-complexity RTL designs.

Using BRT is a straightforward process that does not require any up-front coding, partitioning, or verification changes. Designers use the same methodology they use today to generate the best gates possible. They can then run BRT with a target clock period. BRT automatically moves registers across combinational logic and hierarchy boundaries, returning a gate-level design with the minimal register count needed to achieve target performance. During the optimization process, BRT preserves registers with a "don't touch" attribute.

BRT Dramatically Improves Quality of Results

BRT improves QOR for single-clock applications such as control (finite state machines), datapaths, and mixed control-datapath designs. BRT can also handle any multiple-clock applications that can be optimized separately as single-clock designs. Findings of customer benchmarks on RTL designs as large as 30,000 gates have demonstrated that BRT, on average, improved timing over 15 percent with an increase in area of only 5 percent. In some cases, BRT actually reduced area.

"Synopsys' BRT provides us with a powerful register optimization capability," said Mohamed Soufi, ASIC designer at CAE Electronics. "It optimizes a design well beyond what we can achieve using Design Compiler's logic optimization alone. With BRT, we have seen up to 20 percent better timing and up to five percent less area on several of our RTL designs. We are excited about the results and are expecting to incorporate BRT into our standard ASIC synthesis methodology."

Pricing and Availability

BRT is available immediately as part of Synopsys' Behavioral Compiler tool for Sun, Digital, IBM, and Hewlett-Packard UNIX workstations. Pricing for Behavioral Compiler, which includes Synopsys' most advanced behavioral, RTL, and logic synthesis capabilities, is $155,000 U.S. list.

Synopsys, Inc. (NASDAQ:SNPS) develops, markets and supports high-level design automation models and software for designers of integrated circuits (ICs) and electronic systems. The company pioneered the commercial development of synthesis technology, which serves as the foundation of the company's high-level design methodology. Synopsys offers a comprehensive set of synthesis, simulation, test, and design reuse solutions, which support both Verilog HDL and VHDL. -0-

Note to Editors: Synopsys is a registered trademark of Synopsys Inc. Design Compiler and Behavioral Compiler are trademarks of Synopsys. All other trademarks are the property of their respective owners.

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