New Model First to Support AGP Standard; Logic Modeling's new AGP, USB and Ethernet Models Ease Task of Complying with Industry Standards.

BEAVERTON, Ore.--(BUSINESS WIRE)--Sept. 3, 1996--Logic Modeling of Synopsys, Inc. (NASDAQ:SNPS) today announced the availability of the first commercial model of the emerging Accelerated Graphics Port (AGP) standard, developed by Intel.

Also joining the extensive line of Logic Modeling products supporting industry-standard interfaces are models of the Universal Serial Bus (USB) and Ethernet standards.

The new AGP Target, USB and Ethernet models, like other Logic Modeling models of standard interfaces, simplify the development of complex test benches by creating test stimuli and monitoring and detecting protocol violations. When the models are controlled and synchronized through the Logic Modeling Control Bus, designers can coordinate multiple bus models and control them from a single point through sophisticated command streams.

AGP Development

The Accelerated Graphics Port (AGP) interface is a new bus specification that enables high-performance graphics display capabilities on PCs at mainstream price points. Developed by Intel, AGP uses the Peripheral Component Interconnect (PCI) specification as its starting point. AGP and PCI will coexist in typical systems, with AGP providing an additional connection point from the processor chipset to graphics add-on cards and accelerators.

"Early model availability is important to help designers rapidly adopt new standards and successfully comply with them," said Robbie Wisdom, marketing manager for Synopsys Logic Modeling products. "From the time we introduced the first commercial PCI bus model to the market, our customers have told us that having a complete ready-to-use model of a standard reduces the compliance challenge while enabling designers to shave months off project schedules."

AGP Target Model Tests Compliance

The Logic Modeling AGP Target bus functional model emulates the behavior of an AGP-compliant target device, enabling designers to test their AGP Master Devices against a variety of AGP targets. Also included with the model are an AGP arbitration function and an AGP Monitor which performs protocol checking.

Fully compliant with AGP specification v1.0, the Logic Modeling AGP Target model supports all major features of the specification developed by Intel, including: low/high priority address queues; sideband addressing; low/high priority READ/WRITE queues; configurable queue lengths; 1X and 2X data transfers; AGP protocol checking; bus tracing; GNT pipelining; and AGP and PCI arbitration.

USB Model Supports Key Features

Logic Modeling's USB functional model includes all of the major components of USB specification v1.0. The USB standard is a low-to-medium-speed interface for the connection of PC peripherals, which is rapidly gaining popularity among designers of PC systems.

Designed to perform complete USB protocol checking during simulation, the Logic Modeling USB model comprises actually four models: the USB Host, USB Hub, USB Function and USB Monitor.

The Host/Hub/Function models support all transfer cycles -- control, bulk, interrupt and isochronous; CRC generation and checking, and error generation; NRZI encoding with bit stuffing and error detection via the bus-turnaround timer. Functions supported by the USB Monitor model include bus tracing and protocol checking.

Ethernet Model Handles 100MB Bit Rate

Known as the standard for connecting PC and UNIX workstations on a Local Area Network, Ethernet, or IEEE 802.3, is experiencing increased design activity as companies upgrade systems to higher bit rates. The Logic Modeling Ethernet bus functional model conforms to the IEEE 802.3 standard and performs Ethernet MAC protocol checking during simulation.

All major Ethernet features are supported, including: IEEE 802.3 MAC frame transmit and receive; CRC generation; error generation and checking (incorrect CRC, termination on a non-byte boundary, runts, jabber); LLC Packet generation; and collision detection and signaling.

Availability and Pricing

The AGP Target, USB and Ethernet bus functional models are available in VHDL or Verilog source code format. All three models are verified and supported on all major Verilog and VHDL simulators. First shipments are scheduled for September 1996.

Pricing for the AGP Target model starts at $20,000 (U.S. list price) for a perpetual site-license. Both the USB and Ethernet models are priced at $15,000 (U.S. list price) for a perpetual site-license.

Synopsys offers a number of bus interface models including: PCI, ISA, EISA, SCSI-2, VME, PC Card (16 bit and 32 bit) and MCA. Each of these models conforms to the most current version of the standard.

Synopsys Logic Modeling

Synopsys, Inc. develops, markets and supports high-level design models and software for designers of integrated circuits (ICs) and electronic systems. Through its combination of Logic Modeling hardware and software modeling products, the company offers a comprehensive solution to the simulation model needs of board, system and ASIC designers.

For more information on Logic Modeling products, call 800/346-6335 or send e-mail to [e-mail]. The Internet home page address for Synopsys is http://www.synopsys.com.

CONTACT: Synopsys, Inc.

Diane Landers, 503/531-7651

[e-mail]

or

The Hoffman Agency

Michelle Herman, 408/975-3033

[e-mail]