New Developments in Flip Chip.

A recent study, Flip Chip Markets and Infrastructure Developments, by TechSearch International, Inc. (Austin, TX), investigates the growing market for flip chip ICs and the infrastructure that makes the technology possible. Flip chip has expanded in two major areas: 1) the high-performance needs of the microprocessor, the application specific integrated circuit (ASIC) and the high-end digital signal processor (DSP) device and 2) form factor-die sizes are small and packaging cost must be minimized. New to flip chip technology is the expansion into the interconnect realm previously dominated by wire bond. Expansion into mid-range pin counts represents a shift in the adoption of the technology, which is reflected in cost reductions.

Also new is the introduction of wafer- level packages (WLPs). Many low pin count devices (2 to 50 I/Os) are marketed as WLPs-die that are packaged at the wafer level and do not require underfill for thermal stress management. Many WLPs are fabricated using virtually the same bumping process used for conventional flip chip bumped die. While this low pin count application represents millions of die, few wafers are required because thousands of parts can be produced on a single wafer.

For many companies, the key to the expanded use of flip chip has been the availability of low-cost wafer bumping. Prices from service providers have declined and many merchant bumping operations have introduced or have R&D activities for lead-free bumping methods. Products using lead-free bumps have been also been introduced.

More than 20 companies offer flip chip bonders-each suited for a particular application. New underfill materials, with shorter cure times and improved properties, have been introduced; and developments, such as no-flow and reworkable materials, are promising. For more information on the report, visit www.techsearchinc.com.

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