New Approach to ASIC or ASSP Development from Telairity Semiconductor, a fabless ASIC company.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--Oct. 21, 2002

Telairity Semiconductor Inc., a fabless ASIC company, today announced the Telairity Speed Optimized(TM) (TSO(TM)) design environment that provides a new approach to high-performance ASIC design. The TSO design environment eliminates most of the problems associated with timing closure and signal integrity in ASIC design when using deep submicron (DSM) process technologies and can achieve a 2X performance improvement over conventional methods.

The key to the TSO ASIC design environment is an extensive gallery of pre-engineered, pre-verified IP building blocks. Each IP building block has approximately 1,000 logic gates. The design and layout of the blocks is completed with a custom methodology resulting in designs optimized for high speed. The TSO environment eliminates signal integrity issues such as crosstalk so that customers have "proven," highly reusable IP building blocks. Any digital design can be created with these blocks, seventy-five percent of which are generic and 25 percent are market specific.

"I have spent years with Fujitsu and other semiconductor companies solving COT and ASIC design problems and, as President of the Virtual Socket Interface (VSI) Alliance, I worked with the top semiconductor, EDA and system companies to solve design reuse issues," said Howard Sachs, President/CEO of Telairity. "Those experiences ultimately led me to realize that it was time to look at the ASIC, synthesis and DSM challenges from a new approach -- an approach that would allow engineers to develop complex chips in a much shorter time without sacrificing performance or area. Instead of fixing the shortcomings in existing design tools, the TSO design environment fixes the problems of timing closure and signal integrity up front and provides designers with reusable hard IP building blocks and the methodology and tools to support this solution."

Engineers can develop complex, high-speed designs using pre-engineered blocks referred to as groups and SGEM(TM) point tools from Telairity. With Telairity's ASIC solution, designers no longer have to deal with the time-consuming problems of crosstalk. Careful design and layout of the groups, the small size of the groups at less than 1,000 gates each and the fact that connections for each group are completely contained with the first three wiring layers eliminates local wiring crosstalk. M4 and M5 crosstalk is dealt with easily with existing tools that identify the aggressors and victims and provide enough spacing to eliminate the problems.

Telairity has produced a 400,000-gate test chip using fewer than 50 unique groups to implement a SISD FIR filter, a SIMD FIR filter and a SIMD FFT. This first test chip was used to verify the group IP as well as the methodology and CAD flow. This design went from floor plan to GDSII in one day. New groups are being developed constantly to implement other algorithms. Telairity anticipates a gallery of approximately 1,000 pre-verified groups available in less than one year.

A second DSP test chip, targeted for pre-production release in December 2002, on UMC's 0.18 micron process will operate at greater than 400MHz and achieve a density of better than 50K gates/sq mm.

Telairity Tools

GEM point tools from Telairity augment standard EDA tools, allowing designers to integrate and manage IP.

Telairity Road Map

Telairity is focused on three major engineering design goals: speed, power and time-to-market. Telairity will follow the Telairity Speed Optimized (TSO) design environment launch with the Telairity Power Optimized(TM) (TPO(TM)) environment including PGEM(TM) point tools and the Telairity Time-to-Market Optimized(TM) (TTO(TM)) environment including TGEM(TM) point tools. Each design environment will have unique dedicated tools and associated IP gallery.

Availability

Telairity will be accepting ASIC designs from customers using the TSO ASIC design environment and SGEM tools beginning January 2003. The TPO and TTO design environments, point tools and IP will be available in Q4, 2003. Customers will be able to manufacture ASIC designs using most of the leading processes and design rules available.

About Telairity Semiconductor, Inc.

Telairity Semiconductor Inc. is a fabless ASIC company providing tools, methodology, hard IP and services for developing a broad range of products aimed at high performance, low power and fast time to market applications. The initial applications will be targeted for the communications and consumer markets. Telairity's highly reusable and portable IP and methodology decreases time to market by more than 10X over traditional ASIC approaches and increases performance by more than 2X. Founded in April 2001, by Howard Sachs, President and CEO, Telairity is a privately held company headquartered in Santa Clara, Calif. Jim Meadlock, ex-President/CEO and founder of Intergraph Corporation is the Chairman of the Board for Telairity and lead investor. More information about the company, its products and services is available at www.telairity.com or call 408/764-0270 x104 for more information.

Note to Editors: Telairity Speed Optimized, TSO, SGEM, Telairity Power Optimized, TPO, PGEM, Telairity Time-to-Market Optimized, TTO, and TGEM are all trademarks of Telairity Semiconductor, Inc. Other marks and brands may be claimed as the property of others.