New ATM Quad UNI Continues VLSI's Leadership in High-Speed Network Offerings; VNS67200 Supports ATM Forum's Utopia Level 2 Bus Interface Standard and Multi-PHY Capability.

SAN JOSE, Calif.--(BUSINESS WIRE)--March 25, 1996--VLSI Technology, Inc. today introduced the VNS67200 ATM Quad UNI.

This single-chip device is an innovative four-channel asynchronous transfer mode (ATM) user network interface (UNI) chip which complies with the ATM Forum Utopia Level 2 bus interface standard and includes the Forum's multiple physical interface (Multi-PHY) capability.

The device provides all the digital processing necessary to map ATM to SONET and operates at speeds up to 155.52 megabits per second (Mbps) on each full duplex channel. The ATM Quad UNI offers manufacturers of ATM hubs and switches reduced silicon costs, compact size, and transmission media independence for high-speed local area networks (LAN) or wide area network (WAN) access applications.

"Today, as the industry is rapidly embracing emerging worldwide markets for on-line multimedia switched digital video, voice and data capabilities, ATM-based networks designed specifically to carry this mixed-mode traffic are beginning to proliferate," said Rex Naden, vice president and general manager of VLSI Technology's Network Products Division.

"The VNS67200 meets our customers' need to quickly and inexpensively add high-performance ATM ports. These ports can be included in their LAN hubs, backbone switches and routers or to their WAN multiplexers and edge node equipment offerings. Based on industry estimates, we predict the emerging ATM market will experience strong growth," Naden added.

Product Benefits

Due to the ATM Quad UNI's highly integrated architecture, board space and silicon costs can be significantly reduced. System design time is also reduced because of the product's easy-to-use diagnostics and its microprocessor interface that permits monitoring of complete status information. The VNS67200 is compatible with various physical transmission media such as fiber, twisted pair and coaxial cable.

Compared to discrete single-channel UNI devices, this part reduces pin count and lowers power dissipation. Due to Utopia Level 2 bus Multi-PHY capability, up to eight ATM Quad UNIs or a combination of Quad UNIs and other UNI-compliant devices may be connected to a single bus.

This will allow system designers to achieve further reductions in system pin count and board real estate. Conformity to ATM Forum standards assures full interoperability with other standards-compliant system devices. The part's 5-volt design has been developed to conform directly with the voltage most commonly used in today's network systems.

Product Details

The VNS67200 ATM Quad UNI from VLSI is a four-port UNI that implements the ATM physical layer for broadband ISDN according to ITU recommendation I.432 and ATM Forum UNI specification 3.1. This single-chip, 5-volt device is packaged in a thermally enhanced MQFP package. It provides four independent high-speed, full-duplex serial I/O channels and is designed for use in ATM LAN or ATM WAN access applications.

The VNS67200 design is based on VLSI's modular FSB functional system block architecture and employs VLSI's advanced cell-based design methodology.

Each channel of the ATM Quad UNI operates independently and is typically connected to either a 155.52 megabits per second (Mbps) or 52.84 Mbps clock in order to provide a synchronous optical network (SONET) compatible STS-3c/STS-1 network connection or, optionally, a synchronous digital hierarchy (SDH) compatible STM-1 network connection. Operation at other speeds such as 25.92 Mbps or 12.96 Mbps is also possible.

Each channel includes a Sonet transmission convergence (STC) block that performs the SONET/SDH framing and overhead processing functions, and an ATM cell delineation block (CDB) that performs the ATM cell framing and processing functions. STC block functions include generation and detection of SONET path, line and section overhead including OAM signals, monitoring of network performance and reporting of alarm conditions.

Programmable automatic transmission of alarm indication signals is also provided. CDB transmit functions include ATM cell header error correction (HEC) calculation and insertion, automatic generation of idle cells with user-assigned value when the transmit FIFO underruns and optional scrambling of the cells prior to transmission.

CDB receive functions include programmable automatic filtering of idle cells with an option to have them passed through transparently and an option to have the cells "tagged" as either valid or with errors. These options have been included to facilitate ATM inverse multiplexing applications. Per channel, four-cell deep transmit and receive FIFOs are provided.

Positive-shifted ECL (PECL) differential line driver and receiver circuits are provided at the serial interface of each channel for electrical compatibility with external physical media dependent (PMD) transmission devices such as the Synergy Semiconductor SY69743 quad clock and data recovering transceiver and most other clock and data recovery circuits.

A high performance 50 MHz Utopia Level 2 bus implemented according to the ATM Forum's Multi-PHY requirements provides two independent 16-bit wide parallel data paths for the transfer of ATM cell data between the VNS67200 and the ATM switching system (or "ATM layer device" as it is referred to in the standards).

This interface supports both the polled access method per Section 4.2 of the standard and the direct access method per Section 4.3 of the standard. The ability to supply 8 milliamps of drive current and support 60 pico farad load on each Utopia interface pin ensures full-speed operation in most system designs.

Availability and Pricing

VNS67200 samples will be available from VLSI in April. Initial 1996 per unit prices for production ICs will be US$75 when purchased in 10,000 unit quantities. International pricing will vary.

About VLSI Technology

VLSI Technology, Inc. (Nasdaq:VLSI) designs and manufactures application-specific integrated circuits (ASICs) and application-specific standard products (ASSPs) based on its library of FSB functional system blocks. Targeting its offerings towards the communications, computing, and consumer digital entertainment markets, the company offers its customers advanced system-level integration capabilities.

The company is based in San Jose, California, with 1995 revenues of $720 million, and approximately 3,000 employees worldwide. -0-

Reader product inquiries should be directed to: VLSI Technology, Inc. at 408/434-3100. -0-

Note to Editors: FSB is a trademark of VLSI Technology, Inc.

CONTACT: VLSI Technology, Inc.

Conte Baba, 408/434-7894 (Corporate Communications)

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Don Davis, 408/922-5244 (Public Relations Manager)

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