NIST/SEMATECH collaboration leads to breakthrough on interface state density extraction.

A NIST scientist, in collaboration with researchers at International SEMATECH, recently completed a study of the proper use of capacitance-voltage measurements to extract interface state density of high dielectric-constant (alternate) gate dielectrics for metal-oxide-semiconductor (MOS) devices. Recently, quasi-static analysis has been used to extract the interface state density. The NIST scientist and his collaborators determined that this quasi-static analysis can give incorrect results and that a proper frequency dependent analysis is required.

As the lateral feature sizes of complementary metal oxide semiconductor field-effect-transistors are scaled downward, the gate dielectric capacitance must be increased in order to maintain the same drive current. Historically, this has been accomplished by decreasing the physical thickness of Si[O.sub.2]. As the thickness of Si[O.sub.2] moves toward 1 nm, the gate leakage current becomes unacceptably high. Therefore, numerous alternate dielectrics (e.g., Zr[O.sub.2], Hf[O.sub.2], Hf or Zr silicates, [La.sub.2][O.sub.3]) with dielectric constants greater than Si[O.sub.2] recently have been under intense investigation. These dielectrics typically have a large density of electrically active defects near the silicon substrate (interface states). It is important to be able to measure the density of these defects accurately.

CONTACT: Eric Vogel, [phone]; [e-mail].