NEW RULE SETS FOR LEDA CHECKERS ACCELERATE AND DELIVER.Synopsys Inc. (Nasdaq:SNPS SNPS Space Nuclear Power System ), the technology leader for complex integrated circuit (IC) design, has announced availability of the Altera(R) Coding Style 1.0 policy for Synopsys' LEDA(R) family of hardware description language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) checkers. The policy is a source file that is used to configure the LEDA checkers. It contains critical Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. coding-style rules to minimize design flow bottlenecks and optimize quality of results (QoR) for system-on-a-programmable-chip (SOPC SOPC System on a Programmable Chip SOPC Special Operations Preparation Course SOPC Second-Order Power Control SOPC Shuttle Operations and Planning Center SOPC 1-Stearoyl-2-Oleoyl-Sn-Glycero-3-Phosphatidylcholine SOPC Shaastra Online Programming Contest ) development using Altera programmable logic devices (PLDs) with design-tools such as Synopsys' FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. Compiler II and FPGA Express. The Altera coding style policy for LEDA is comprised of a special set of coding-style rules derived from the 300+ rules, pre-packaged with Synopsys' LEDA programmable HDL checker. These rules check for common mistakes and poor design practices such as treatment of module inputs and outputs, resets, inadvertent inference of latches, gating of clocks, etc. Altera determined these rules to be critical for ensuring a smooth design flow and optimum performance when targeting its PLD architectures. Synopsys also worked with Altera to customize error-messages and documentation for these rules, thus giving designers additional guidance for optimizing different tool-execution options and selecting microarchitecture-level component. The Altera Coding Style 1.0 policy will be available December 2000 and can be downloaded free of charge from the Synopsys web site to current LEDA licensees. |
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