NEC Electronics Inc. Announces Major OEM Design Wins for 200 MHz 64-Bit MIPSr RISC Microprocessor; VR4400-200 CPU Selected by Pyramid, Concurrent.LAS VEGAS--(BUSINESS WIRE)--Nov. 14, 1994--In a significant win for the MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. reduced instruction set computing Noun 1. reduced instruction set computing - (computer science) a kind of computer architecture that has a relatively small set of computer instructions that it can perform reduced instruction set computer, RISC (RISC RISC in full Reduced Instruction Set Computing Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s. ) architecture, NEC (NEC Corporation, Tokyo, www.nec.com, www.necus.com) An electronics conglomerate known in the U.S. for its monitors. In Japan, it had the lion's share of the PC market until the late 1990s (see PC 98). NEC was founded in Tokyo in 1899 as Nippon Electric Company, Ltd. Electronics Inc. today announced two major OEM (Original Equipment Manufacturer) The rebranding of equipment and selling it. The term initially referred to the company that made the products (the "original" manufacturer), but eventually became widely used to refer to the organization that buys the products and design wins for its 200 megahertz One million cycles per second. See MHz. MegaHertz - (MHz) Millions of cycles per second. The unit of frequency used to measure the clock rate of modern digital logic, including microprocessors. (MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. ) VR4400 RISC microprocessors. The two, Pyramid Technology Pyramid Technology was a computer company that produced a number of RISC-based minicomputers at the upper end of the performance range. They also became the second company to ship a multiprocessor Unix system (branded DC/OSx), in 1985, which formed the basis of their product line Corporation and Concurrent Computer Corporation  This article or section is written like an .Please help [ rewrite this article] from a neutral point of view. Mark blatant advertising for , using . , have independently agreed to purchase an undisclosed number of NEC s VR4400-200 RISC microprocessors for use in their high- performance computing systems. Both design wins are follow-ons to earlier partnerships involving VR4400 microprocessors with internal clock speeds of up to 150 MHz. First introduced in 1992, NEC s VR4400 family has expanded to include 100 MHz, 133 MHz, 150 MHz and now 200 MHz versions. The new VR4400-200 features NEC s advanced 0.35-micron process technology for improved performance and a smaller die size. "These design wins, from three of the leaders in high-end computing systems, speak highly of the performance advantages of the MIPS RISC architecture and of the quality of NEC's 200 MHz VR4400 product," said Basheer Ahmed, product marketing manager, microprocessors, for NEC Electronics Inc. "These design wins are also a clear vote of confidence in NEC's ability to produce quantities of the 200 MHz VR4400 RISC microprocessor." Pyramid has designed the VR4400-200 into its Nile Series symmetric multiprocessing systems. The Nile system relies on the VR4400-200 to provide the processing power, openness and scalability required to enable more than 1,000 transactions per second In a very generic sense, the term Transactions Per Second refers to the number of atomic actions performed by certain entity per second. In a more restrictied view, the term is usually used by DBMS vendor and user community to refer to the number of database transactions performed on a single system or, in cluster configurations, support for up to 10,000 concurrent users. The MIPS RISC microprocessor is one of the most widely used, high- performance CPUs in the open systems industry today, delivering unsurpassed throughput for our clients needs, said Boyd Pearce, vice president of marketing for Pyramid Technology Corp. Throughout our long-standing relationship with NEC, Pyramid has achieved outstanding reliability and availability of these processors at competitive costs. At Concurrent, the VR4400-200 is slated for use in the company s forthcoming enhanced models of its MAXION multiprocessor system. The MAXION multiprocessor system is a high-end, symmetric multiprocessing system targeted for a wide range of real-time applications, including simulation and training; data acquisition, analysis and control; and weather and airspace management. The MAXION system's performance and linear scalability together with its fault tolerant architecture also make the system ideal for demanding financial, wagering and gaming and interactive multimedia applications. Today, Concurrent's MAXION multiprocessor system is available with NEC's VR4400-150. Concurrent will enhance the MAXION system's performance with the VR4400-200. The upgraded MAXION multiprocessor system is slated for general availability in the first quarter of 1995. "Concurrent selected NEC as its vendor of choice for the MIPS RISC microprocessor on the basis of product quality, leading-edge technology and superior commitment to its customers," said Robert Kovarcik, Concurrent's vice president of Manufacturing. "NEC has continued to offer price/performance competitive products while maintaining aggressive reasearch and development investment." Features and Benefits The VR4400 operates at either 3.3- or 5-volts with internal clock speeds up to 200 MHz. With more than two million transistors on a chip, the VR4400 CPU CPU in full central processing unit Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. is ideal for workstation, high-end PC and multiprocessing system applications. The VR4400 RISC microprocessor, based on the MIPS RISC architecture, implements such advanced techniques as superpipelining, a pipe-lined floating- point unit, two-level cache memory and a high-performance on-chip translation lookaside buffer A Translation Lookaside Buffer (TLB) is a CPU cache that is used by memory management hardware to improve the speed of virtual address translation. A TLB has a fixed number of slots containing page table entries, which map virtual addresses onto physical addresses. (TLB TLB - Translation Look-aside Buffer ). In addition, the microprocessor s internal cache and Memory Management Unit (MMU (Memory Management Unit) The part of the computer that governs memory access. Either part of the CPU chip or housed on separate chips, the MMU controls memory partitions and virtual memory. See memory and virtual memory. MMU - Memory Management Unit ) offer a high performance solution for handling large-address-space tasks and a large number of users. In addition, the CPU features 64-bit integer and floating-point operations, registers and virtual addresses. On-chip primary cache memory includes 16K bytes of instruction cache and 16K bytes of data cache. Simulation of the VR4400 processor indicates performance levels of 117 SPECint92 and 131 SPECfp92. The MIPS Architecture NEC licenses the MIPS RISC technology from MIPS Technologies, Inc., a wholly owned subsidiary Wholly Owned Subsidiary A subsidiary whose parent company owns 100% of its common stock. Notes: In other words, the parent company owns the company outright and there are no minority owners. of Silicon Graphics, Inc. Using this technology, NEC manufactures VR-Series high-performance microprocessors. The VR4400-200 joins the VR4200, VR4000 and MR4400 microprocessors to comprise NEC s 64-bit RISC offering. The VR4400-200 chip is one of the fastest microprocessors available today and is used in multiprocessor systems, workstations and high-end personal computers. The MIPS architecture implements techniques such as superpipelining, a pipelined floating-point unit, two-level cache memory and a high-performance on- chip translation lookaside buffer (TLB). In addition, cache and a memory management unit (MMU) offer high-performance in handling large-address-space tasks. About NEC Electronics NEC Electronics Inc., headquartered in Mountain View, Calif., manufactures and markets an extensive line of electronic products including ASICs, microprocessors and microcontrollers, digital signal processors (DSPs), memories and components. The company operates a 676,000 square-foot manufacturing facility in Roseville, Calif. NEC Electronics Inc. is an affiliate of NEC Corporation (NIPNY), a $35 billion international manufacturer of computer, communications and semiconductor products. -0- Note to Editors: See NEC Electronics Inc. at COMDEX The former, premier computer trade show in the U.S. Although it grew into an end user event, it was originally created for dealers and distributors (it was the COMputer Dealers EXposition). Booth L1446. MIPS is a registered trademark of MIPS Technologies Inc. VR4400, VR4000 and VR4200 are trademarks of NEC Corporation. Concurrent Computer Corporation is a trademark of Concurrent Computer Corporation. MAXION is a trademark of Concurrent Computer Corporation. Nile is a trademark of Pyramid Technology Corporation. CONTACT: NEC Electronics Inc.
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