NEC Electronics Europe Standardizes On Synopsys Physical Synthesis; Chip Architect Crucial to Taping Out 3.8 Million Gate 622 MHz Telecommunications Chip.

Business Editors/High Tech Writers

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Oct. 8, 2001

Synopsys, Inc. (Nasdaq:SNPS), today announced that NEC Electronics (Europe) GmbH has successfully utilized Synopsys' Chip Architect physical design planner to tape out a 3.8 million gate, 622Mhz telecommunications ASIC chip, using NEC's 0. 18-micron process with ball grid array packaging. By adopting Chip Architect in their flow, NEC was able to substantially reduce design time by several weeks. Following this successful engagement, NEC has integrated Chip Architect into its standard design kit for 0.18 micron and below system-on-a-chip (SoC) ASICs.

Faced with the challenge of implementing a complex, multimillion-gate chip for a European telecommunications customer, NEC turned to Synopsys' Physical Synthesis for the solution. NEC designers, in collaboration with their customer, used Chip Architect for design planning, partitioning and analysis, before performing optimization for timing closure with Physical Compiler.

"Chip Architect allowed us to create a floorplan that successfully incorporated all the key NEC-specific physical design constraints, power plan and macro placements requirements, and it allowed us to do timing and routability analysis at an early stage before we committed to block level implementation," says Thomas Langfermann, manager of European Design Centers for NEC Electronics Europe GmbH. "Initially, our design flow did not include Physical Compiler, but we ended up using it to help us with timing closure problems. Chip Architect saved us several weeks on the schedule. We plan to use both tools for future complex digital designs."

"NEC is clearly a leader in high performance ASICs. We are extremely pleased that Physical Synthesis has become a standard part of NEC's design flow," said Sanjiv Kaul, senior vice president and general manager for Synopsys Physical Synthesis business unit. "It is indicative of the momentum Synopsys' Physical Synthesis enjoys, propelled by successes such as this leading edge ASIC design."

About Physical Synthesis

Synopsys' Physical Synthesis has an unprecedented rate of customer success in EDA industry history. With over 250 customer tape outs and dozens of companies standardizing on Synopsys' Physical Synthesis, it has become solution for designing complex, deep submicron chips. It has been instrumental in saving customers weeks or months in schedules on some of the most complex designs in the industry. Synopsys' Physical Synthesis overall design flow includes Physical Compiler(TM), Route Compiler standard cell router, Chip Architect design planner, ClockTree Compiler clock tree synthesis and FlexRoute top-level router.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys and Physical Compiler are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.