Motorola Unveils Industry's Most Powerful DSP Architecture; Digital Signal Processor Delivers 80 MIPS Performance to Enable New Applications.

AUSTIN, Texas--(BUSINESS WIRE)--Sept. 25, 1995--Motorola's (NYSE:MOT) Digital Signal Processing (DSP) Division, part of Motorola's Microcontroller Technologies Group, today unveiled its new 24-bit DSP56300 core architecture, the immediate availability of the DSP56300 family's first offering, the DSP56301, and also disclosed plans for several additional family members.

The DSP56300 architecture offers users unsurpassed performance in terms of raw Million Instructions Per Second (MIPS), rich instruction set and low power consumption. The one-instruction-per-clock-cycle DSP56300 architecture is an industry first and sets the standard for performance in a new generation of signal processing-hungry applications such as wireless, telecommunications and multimedia.

"Motorola's DSP56300 is the only programmable family with this magnitude of performance," said Jim George, corporate vice president and general manager of Motorola's DSP Division. "This core-based architecture will be offered in a plethora of products over the next several years. We project that the DSP56300 family derivatives will enable a new level of system performance over their life cycle."

The DSP56300 architecture is the first programmable DSP product to provide a true single-clock-cycle execution, which effectively doubles the number of instructions executed without increasing clock speed. Competitive products currently require two or more clock cycles per instruction cycle. The DSP56300 architecture also retains software compatibility with the popular DSP5600 family.

The DSP56301 is the first implementation of this DSP56300 architecture. The DSP56301, initially available at 66 MIPS and 66 MHz, will offer users this new level of performance at 80 MIPS, 80 MHz in Q2 of 1996. Motorola's DSP56301 has secured designs with leading customers in applications such as wireless infrastructure, videoconferencing, multi-line voice/data/fax processing, Asynchronous Digital Subscriber Loop (ADSL), Asynchronous Transfer Mode (ATM) and Integrated Services Digital Network (ISDN), to name a few.

Current customers include British Telecommunications (Martlesham Heath, United Kingdom), Dialogic Corporation (Parsippany, NJ) and Motorola GSM Products Division (Swindon, England). "We intend to use the DSP56301 in our future videoconferencing products - it's an ideal chip for audio compression/decompression and advanced telecommunications control functions," said Graham Mills, manager, Advanced Multimedia Services, British Telecommunications.

Low power consumption is a key element in the DSP56300 family's performance. In addition to the richness of the instruction set which reduces MIPS, several power saving features were integrated into the DSP56300 family. The products utilize low power, fully static CMOS designs, allowing users to throttle internal clock speed from 80 MHz to zero.

Initial versions of the DSP56300 family run at 3.0 to 3.6 volts; Motorola plans to lower power consumption to 2.7 and 1.8 volts in the future. In addition to traditional Stop and Power Down modes, an intelligent power management system automatically powers down unused memories, peripherals and unused core logic on an instruction by instruction granularity.

Rich Instruction Set

The DSP56300 family provides a highly parallel instruction set which control four concurrent execution units: the Arithmetic Logic Unit (ALU), the Address Generation Unit (AGU), the Program Control Unit (PCU), and the Direct Memory Access Unit (DMA). The Data ALU features a fully pipelined 24x24 bit parallel multiply-accumulator which is further enhanced with a 56-bit parallel barrel shifter providing single-clock-cycle throughput. The barrel shifter supports efficient data stream parsing, which reduces software overhead. Conditional ALU instructions have also been added, lowering MIPS requirements.

The instruction cache support is user-transparent, provides hardware cache management, and implements no access penalty for cache misses. It configures 1K word of PRAM to instruction cache and allows the user to lock or flush individual sectors.

The DSP56301 contains a total of 4K word program memory (PRAM), which can be reconfigured to provide 3K word of PRAM and 1K word of instruction cache. The instruction cache can lower the requirements for expensive high-speed external memory. In addition, there is 4K word of data memory on the DSP56301, which is split into 2K word of X memory and 2K word of Y memory.

External Buses and Extensive Peripherals

The DSP56300 external bus supports glueless connection to external DRAM, SRAM, synchronous SRAM, ROM and peripherals on a 24-bit address and 24-bit data bus. Four user programmable address attributes are provided to eliminate external logic and allow interfacing to a wide variety of memories and peripherals.

In addition, Motorola is the first to develop a complete glueless interface to the Peripheral Controller Interface (PCI) bus and has placed this feature on-board the DSP56301. The PCI bus allows faster, more efficient data transferring by its integration onto the chip.

DSP56301 Development Tools

Motorola currently has several robust development tools available in addition to its silicon offering. A cross linker, assembler and simulator (CLAS) software development package, a `C' compiler and a DSP56301 Application Development System (ADS) are available.

The DSP56301 is supported by many third party developers, including Domain Technologies, Inc. (Plano, TX), Momentum Data Systems, Inc. (Costa Mesa, CA), Sonitech International (Wellesley, MA), Spectron Microsystems (Santa Barbara, CA) and Spectrum Signal Processing, Inc. (Burnaby, B.C., Canada).

DSP56300 Family Plans

Motorola intends to proliferate its 24-bit DSP56300 family with a complete spectrum of programmable DSPs. Motorola will continue to push the performance of the DSP56300 family to 100 MIPS/MHz in the months to come. In addition, Motorola DSP is developing a next-generation family of the DSP56300 architecture optimized for low cost, high volume applications.

Motorola is currently targeting wireless subscriber applications with this next-generation family, which will also feature even lower power consumption, lower voltage and high processing power. This new product family will be available in 1996.

Having 1994 worldwide sales of $6.9 billion, Motorola's Semiconductor Products Sector is the largest U.S.-based broad line supplier of semiconductors with a balanced portfolio of more than 50,000 devices. Motorola is one of the world's leading providers of wireless communication, semiconductors and advanced electronic systems and services.

Major equipment businesses include cellular telephone, two-way radio, paging and data communications, personal communications, automotive, defense, and space electronics and computers. Communication devices, computers and millions of consumer products are powered by Motorola semiconductors. Motorola's 1994 sales were 22.2 billion. -0-

Note to Editors: Photos are available upon request.

CONTACT: Cunningham Communication, Inc.

Michele Healey, 408/764-0785

or

Motorola DSP Marketing, 512/891-2030