Mosel Vitelic to make page-mode extended data output standard on all high-speed DRAMs.

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 14, 1995--To deliver the fastest possible access times from cost-effective conventional-architecture DRAMs for upper-midrange performance Windows graphics accelerator frame buffers, all future Mosel Vitelic DRAMs with 50-nanosecond and faster access times will include page-mode EDO (Extended Data Out-column addresses are latched) output capability as a standard feature.

The memory speed-to-price ratio is critical to graphics accelerator manufacturers; page mode memory cycle time is vital to the accelerator performance equation, yet total frame buffer memory (usually 1 or 2 Mbytes) often represents the bill of materials' most expensive item. Key configurations for this market are 256K x 8 and 256K x 16.

Mosel Vitelic's decision to make EDO as a standard DRAM feature is key to expanding its position as the top memory supplier to the upper-midrange Windows accelerator market segment.

Over the last three years, Mosel Vitelic has facilitated frame buffer cost reduction through a succession of cost-effective high-sped DRAMs. These DRAMs have helped displace video RAM (VRAM) as the dominant memory architecture for PC graphics accelerators.

DRAMs with EDO latch column addresses to allow for faster accesses without violating output-data timing constraints. With EDO, output data remains valid even when the column address strobe (CAS) goes HIGH. Mosel Vitelic's First DRAM with EDO, the V53C8257H, was announced last year. The V53C8257H, a 256K x 8 DRAM which also incorporates a burst counter, has user-selectable burst mode.

According to Rajit Shah, director of world-wide marketing for the Taiwan-headquartered memory chip maker, "EDO delivers approximately five nanoseconds faster page-mode cycle times in DRAMs for Windows accelerator frame buffers. For example, successive accesses to contiguous addresses on a single memory page can occur every 20, rather than 25, nanoseconds. During graphics intensive operation, that extra 5 nanoseconds increases the volume of data bus between the frame buffer and the controller by 20 percent."

First In Speed

Although Mosel Vitelic's fast DRAMs are conventional in architecture, they are the fastest in the industry. The company accomplishes this by utilizing state of the art design techniques to fit the requirements of accelerator frame buffers.

Mosel Vitelic's Portfolio

Mosel Vitelic's strategy is to serve the data storage, telecommunications, computer peripheral and printer markets with high-volume products, while supplying innovative niche products for graphics accelerator and CE-ROM drive applications. In addition to DRAM and VRAM, Mosel Vitelic's principal products include fast SRAMs.

Mosel Vitelic applies state-of-the-art design techniques to manufacture competitive high-volume specialty products for the mid- to high-performance PC marketplace. This strategy provides economies of scale in manufacturing and sales and allows Mosel Vitelic to insulate itself from the more vulnerable main-memory market.

CONTACT: Mosel Vitelic, San Jose

Esther Hsieh, 408/433-6025

Don Tuite, 415/691-1488