Monterey Design Targets Multi-million Gate Nanometer Chips With Latest Release; Recent Customer Tapeouts Prove Monterey's Value for Multi-million Gate SoC Designs.

Business Editors/High Tech Writers

SUNNYVALE, Calif.--(BUSINESS WIRE)--Dec. 2, 2002

Monterey Design Systems today announced the latest release of the company's IC Wizard(TM) hierarchical design planner, Sonar(TM) physical synthesis and prototyping tool, and Dolphin(R) physical implementation system.

Release 2.5 of the Monterey tool set is the fastest, highest capacity, and most functionally complete product line ever offered by the company. Recently announced tapeouts and target designs include consumer electronics chips, streaming data processors, and switch fabrics ranging in size from one million to 20 million gates on process technologies of 150, 130, and 90 nanometers.

Link to recent customer announcements:

http://www.montereydesign.com/newsevents/press.htm

"TeraChip uses Monterey exclusively for hierarchical design planning and physical implementation. With our unique layout methodology and Monterey tools, we closed the physical design of a very complex high-end chip, covering all deep sub-micron signal integrity issues, with a minimum of engineering effort," said Gideon Paul, vice president of R&D at TeraChip Corporation. "Using Monterey tools, we were able to achieve the impossible - the implementation of a unique switch fabric architecture combining high bandwidth and high functionality on one compact chip, in record time. This switch fabric solution, driven by Monterey tools, enabled our customers to implement elegant simplified solutions at significantly lower cost."

Hierarchical design planning

Complex SoC's today contain hundreds of memory, analog, and mixed signal blocks. Gate-level design planners are not geared to handle designs with many hard blocks. Prior releases of IC Wizard were optimized to deal with hundreds of hard blocks, but worked best when standard cells were clustered into blocks at the top level. IC Wizard 2.5 has been enhanced to support un-clustered standard cells at the top level. Today, IC Wizard is the only hierarchical design planner available that can handle multi-million gate chips containing hundreds of blocks and millions of standard cells simultaneously.

For very large blocks that contain more than a million gates and are instanced multiple times in a design, it is often advantageous to choose a single implementation of the block in order to reduce the time and effort needed to implement the block. IC Wizard automatically configures the timing and physical constraints taking into consideration all instantiations of the block within the context of the chip-level design plan and resulting in a faster and more optimized implementation.

IC Wizard is the only hierarchical design planner that handles an unlimited number of levels of hierarchy. Gate-level design planners restrict designs to two levels of hierarchy. This works well for digital logic design, but is overly restrictive when dealing with complex SoC designs that may incorporate hundreds of memory, analog, and mixed signal elements. IC Wizard enables the user to optimize the physical hierarchical structure by clustering elements to create new levels of hierarchy, by flattening structures to remove levels, or by moving entire branches from one part of the hierarchical tree to a different part. It also tracks all changes so that comparisons can be made between different structures.

Link to IC Wizard product page: http://www.montereydesign.com/products/icwizard.htm

"IC Wizard is a complete design planner that expertly handles hierarchical designs," continued Paul of TeraChip. "Using IC Wizard, we were able to close, in a very short time, our highly complex chip interconnect as well as detailed blocks and pin placement."

Physical synthesis, prototyping, and implementation

The run times of Sonar and Dolphin 2.5 have been improved by a factor of 2X with no penalty in quality of results. On the recently announced Linux port, Sonar and Dolphin run five times faster than prior releases. Benchmarks run on customer designs show that a million gate chip can be taken from netlist to GDSII in less than twelve hours.

Sonar and Dolphin 2.5 offer improvements in circuit performance of 10-15% by incorporating new physical synthesis and placement algorithms. This new functionality has been added without any degradation in runtime.

Memory utilization has been improved to handle designs twice as large as prior versions increasing the flat capacity beyond 5 million gates. When combined with the hierarchical capabilities in IC Wizard, capacity scales upwards of 100 million gates.

Support for flip-chip technology has been introduced in release 2.5. The I/O bump pattern is imported into Dolphin and the router makes all connections from the I/O cells automatically.

Parasitic extraction in 2.5 has been improved such that Dolphin now correlates more closely to 3-D field solvers than industry standard chip-level sign-off extractors. The results from Dolphin extraction may be written out in SPEF and DSPF formats.

With release 2.5, ECO's may now be restricted to metal layers without changing the underlying polysilicon or diffusion layers. During the initial construction of the chip, the user has the ability to include spare cells in the design that may be used for subsequent ECO's. If the ECO does not require major structural changes, then it may be implemented by using the spare cells and making changes to routing on metal layers.

Link to Sonar product page: http://www.montereydesign.com/products/sonar.htm

Link to Dolphin product page: http://www.montereydesign.com/products/dolphin.htm

"Monterey Sonar and Dolphin were instrumental in our ability to deliver the T64 switch fabric chip set in record time," said Guntram Wolski, director of VLSI at Tau Networks. "We have seen significant improvements in the speed of the Dolphin 2.5 router and, based on our past success with Dolphin, we anticipate superior die size and time to market results on our next generation of switch fabric products."

"Customer feedback on our prior product releases was very consistent," said Dave Reed, vice president of marketing at Monterey. "They were very satisfied with our technology, our approach, and the functionality and stability of our products. We decided that we could best serve our customers by concentrating on speed, capacity, and quality of results. With release 2.5, our customers can not only achieve the excellent results that they have come to expect from Monterey, but they can get those results faster and on bigger designs than ever before."

Availability

Release 2.5 of all Monterey products is available immediately on all supported hardware platforms. Pricing for a one-year, time-based license starts at $148,000 (U.S.) for IC Wizard, $105,000 (U.S.) for Sonar, and $400,000 (U.S.) for Dolphin. Please check with your local sales representative for international pricing.

About Monterey Design Systems

Monterey Design Systems provides electronic design automation software that enables integrated circuit designers to take their circuits from completed logic design to manufacturing ready output. Built to handle the most demanding semiconductor process requirements, the company's products - IC Wizard(TM) hierarchical design planner, Sonar(TM) physical prototyper, and Dolphin(R) physical implementation system - combine to provide the most streamlined physical design flow on the market. Monterey Design Systems is privately held and partners with other leading EDA companies, such as Cadence (NYSE:CDN - news) and Synopsys (Nasdaq:SNPS - news), to ensure interoperability in all existing design flows. Key customers include LSI Logic, STMicroelectronics, Fujitsu Limited, Flextronics Semiconductor, and NEC Electronics. Monterey Design Systems is located at 894 Ross Drive, Sunnyvale, CA 94089-1443, tel: [phone], fax: [phone], http://www.montereydesign.com

Monterey, Monterey Design Systems, Dolphin and System-Driven Physical Design are registered trademarks and IC Wizard and Sonar are trademarks of Monterey Design Systems. All other trademarks and registered trademarks are the property of their respective owners.