Monterey Design Systems Delivers Production-Hardened Dolphin 2.0; Revolutionary Technology Matured Into Revolutionary Product.Business Editors/High Tech Writers
SUNNYVALE, Calif.--(BUSINESS WIRE)--Dec. 3, 2001
Monterey Design Systems(R) today announced version 2.0 of its Dolphin(R) physical implementation system. This new version of Dolphin provides all of the capabilities necessary for designers to complete their physical implementation in a single tool -- significantly reducing the complexity of their design flow.
The result of more than 40 man-years of development, an extended period of beta testing (programming) beta testing - Testing a pre-release (potentially unreliable) version of a piece of software by making it available to selected users. This term derives from early 1960s terminology for product cycle checkpoints, first used at IBM but later standard throughout the , and an intensive quality assurance effort, Dolphin 2.0 includes more than 30 new features. Significant new capabilities include ECO E·co , Umberto Born 1932.
Italian writer best known for his novels, including The Name of the Rose (1981). He has also written extensively on semiotics and British and American popular culture. , interactive wire editing, built-in silicon-correlated extraction, automatic clock-skew management, cross-talk aware timing analysis, cross-talk driven routing, and improved ease of use. The QA effort included running a suite of 29 previously taped-out customer designs from netlist through tapeout with each weekly build.
"The release of Dolphin 2.0 is a major milestone for Monterey," said Tom Kozas, product marketing director at Monterey Design. "Our customers have been using beta versions of this release to complete designs for the last six months. With the production release of version 2.0, Dolphin is ready for the most demanding of customer environments."
Pricing and Availability
The production release of Dolphin 2.0 will be shipped to customers starting December 10th. It is supported on 32 and 64 bit workstations from Sun and HP. Pricing begins at $400,000 per year (U.S. list price). Current Dolphin customers will receive Dolphin 2.0 as part of their service agreement.
New Features of Version 2.0
-- Support for OLA libraries including the following -- Cell function -- Pre-layout cell delay -- Post-layout cell delay and interconnect delay -- Support for conditional delays in .lib library
-- Support for new antenna constructs
-- Accumulative LEGACY, ACCUMULATIVE. An accumulative legacy is a second bequest given by the same testator to the same legatee, whether it be of the same kind of thing, as money, or whether it be of different things, as, one hundred dollars, in one legacy, and a thousand dollars in another, or whether analysis
-- Analysis including vias
-- Analysis including diffusion area separate from pin area
-- Current limits by wire widths
-- Angular spacing rules
-- Conformal con·for·mal
1. Mathematics Designating or specifying a mapping of a surface or region upon another surface so that all angles between intersecting curves remain unchanged.
2. dielectric layers and passivation passivation
the final stage in instrument manufacture, passing the finished instruments through a bath of nitric acid which removes foreign particles and promotes the formation of a protective coating of chromium oxide. layers
-- Width dependent wire resistance
-- Temperature dependent wire resistance
-- Support for TCL See Tcl/Tk.
Tcl - Tool Command Language API access to the design database
Logic Optimization Logic optimization a part of logic synthesis, is the process of finding an equivalent representation of the specificied logic circuit under one or more specified constraint. Generally the circuit is constrained to minimum chip area meeting a prespecified delay.
-- Easier-to-use control over the internal optimization and
-- Support for setup range fixing
-- New buffering algorithms
-- New re-synthesis capability
-- New sizing algorithms
-- New slack allocation and area recovery algorithms
-- Automatic useful skew (1) The misalignment of a document or punch card in the feed tray or hopper that prohibits it from being scanned or read properly.
(2) In facsimile, the difference in rectangularity between the received and transmitted page.
-- Optimization using propagated clock
-- Post detail placement hold fixing using propagated clock
-- New scan reordering re·or·der
v. re·or·dered, re·or·der·ing, re·or·ders
1. To order (the same goods) again.
2. To straighten out or put in order again.
3. To rearrange.
-- Incremental placement to support ECO
-- Support for OLA Noun 1. ola - leaf or strip from a leaf of the talipot palm used in India for writing paper
Corypha umbraculifera, talipot, talipot palm - tall palm of southern India and Sri Lanka with gigantic leaves used as umbrellas and fans or cut into strips for libraries including
-- Cell function
-- Pre-layout cell delay
-- Post-layout cell delay
-- Interconnect delay
-- New .lib model generation for hierarchical flow
-- Support for ECO on clock nets
-- New skew analysis reports
-- New skew balancing between primary and generated clocks
-- New balanced routing
-- New ease-of-use features
-- Point to point routing
-- Region based ripup and reroute
-- Support for angular spacing rules
-- Variable wire width for EM and power routing
-- Variable wire spacing for crosstalk avoidance
-- Support for accumulated antenna analysis mode
-- Support for diode insertion to fix antenna violations
Signal Integrity - Crosstalk
-- Cross talk aware delay calculation
-- Automatic cross talk avoidance and repair
Signal Integrity - Electromigration
-- Support for wire sizing to resolve electromigration on clock
-- Current limits/wire widths
-- Conformal dielectric layers
-- Width dependent wire resistance
-- Temperature dependent wire resistance
-- Process Variation
-- Incremental Placement
-- Incremental Route
-- Clock ECO
-- Cross talk ECO
Dolphin employs Monterey's patented Global Design Technology. Global Design Technology provides for simultaneous optimization of timing, area, and routability while performing logic optimization, placement and routing, resulting in a non-iterative, predictable physical design flow.
In contrast, competing design flows take a sequential approach. Designers are required to identify, analyze, and fix problems using several applications. This often leads to numerous time-consuming iterations because the optimizations performed by one tool can cause problems for other tools in the flow.
About Monterey Design Systems
Monterey Design Systems provides the industry's only System-Driven Physical Design solution, giving customers the fastest and most advanced System to GDSII GDSII Graphic Design System II approach for deep sub-micron SoC design. The company combines design planning, physical prototyping, sign off and automated physical implementation to provide a physical design flow that begins at the system level and produces a manufacturing ready layout. Monterey Design Systems is privately held and partners with leading EDA companies such as Cadence (NYSE NYSE
See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ) and Synopsys (Nasdaq:SNPS SNPS Space Nuclear Power System ) to ensure interoperability in ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and COT design flows. Monterey Design Systems is located at 894 Ross Drive, Sunnyvale, CA 94089-1443, tel: 408/747-7370, fax: 408/747-7377, http://www.montereydesign.com/.
Note to Editors: Monterey and Monterey Design Systems are registered trademarks and System-Driven Physical Design is a trademark of Monterey Design Systems. All other trademarks and registered trademarks are the property of their respective owners.